Sealing Ring Layout for Thick Top Metal Without Chip Area Growth
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Solution Overview
Problem
Increasing the thickness of the uppermost conductor in a semiconductor device leads to decreased adhesion of the polyimide film, necessitating an increase in conductor width, which in turn increases the chip area.
Innovation Solution
The semiconductor device design includes a sealing ring with conductors stacked such that the inner peripheral edge of the uppermost conductor is positioned inward, allowing for the utilization of space under the conductor for additional circuit elements or structures, thereby maintaining a smaller chip area despite increased conductor width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the uppermost conductor is increased, then the adhesion of the polyimide film decreases, but increasing the width of the conductor is necessary to ensure adhesion
Solution Approach 1:
The patent applies dimensionality change by positioning the inner peripheral edge of the uppermost conductor inward relative to the inner peripheral edges of lower conductors, creating a stepped configuration. This utilizes the vertical dimension and spatial arrangement to allow the polyimide film to wrap around and adhere to the thicker uppermost conductor from multiple directions, ensuring adhesion without requiring increased conductor width and thus preventing chip area expansion.
Solution Approach 2:
The patent implements nesting by having the uppermost conductor positioned within the horizontal footprint of the conductors below it, creating a nested or stepped structure. This allows the polyimide film to effectively envelop the conductor stack, providing adequate adhesion area for the thicker uppermost conductor without increasing the overall chip area, as the conductors are nested within each other's projected area.
2Reliability
If the width of the uppermost conductor is increased to ensure polyimide film adhesion, then the chip area increases
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension and stepped horizontal positioning. The uppermost conductor is positioned inward in plan view, creating a stepped structure that allows the polyimide film to wrap around the conductor from multiple angles. This provides sufficient adhesion area for thick conductors without requiring increased conductor width, thereby maintaining constant chip area while ensuring reliable polyimide film adhesion.
Solution Approach 2:
The nested configuration of conductors, where the uppermost conductor is positioned within the horizontal footprint of lower conductors, enables the polyimide film to effectively envelop the entire conductor stack. This nesting arrangement provides adequate surface area for adhesion through the wrapped configuration rather than through increased conductor width, thus preventing chip area expansion while maintaining reliable adhesion.
Data Source
AI summary
A semiconductor device capable of suppressing an increase in chip area due to the widening of a conductor located on the topmost layer of a sealing ring is provided. The semiconductor device includes a semiconductor substrate and the sealing ring. The sealing ring is formed on a periphery of the semiconductor substrate in a plan view. The sealing ring includes a plurality of conductors stacked on each other. Each of the plurality of conductors has an inner peripheral edge and an outer peripheral edge. An inner peripheral edge of a first conductor, which is located on the topmost layer of the plurality of conductors, is positioned more inward than any of inner peripheral edges of a plurality of second conductors located below the first conductor in a plan view.