Multi-Layer Sealring Wiring for Semiconductor Reliability
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Solution Overview
Problem
Current semiconductor devices with sealrings face challenges in achieving both reliability and miniaturization, as the proximity of sealring wirings to pads or other components can lead to stress-induced cracks and reliability degradation due to thermal expansion differences, and existing designs often compromise on size reduction to maintain reliability.
Innovation Solution
The semiconductor device incorporates a sealring structure where the uppermost sealring wiring is positioned further outward and has a smaller width than the wiring layer below it, increasing the distance between the sealring and adjacent components, thereby reducing stress and enhancing visibility for inspection, while maintaining or reducing the overall device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the sealring wiring is positioned closer to pads or other components to reduce device size, then miniaturization is achieved, but stress-induced cracks and reliability degradation occur due to thermal expansion differences
Solution Approach 1:
The patent applies dimensional change by transitioning from a single-layer sealring wiring to a multi-layer laminated structure. The first sealring wiring is formed in one wiring layer and the second sealring wiring is formed in another wiring layer, creating a three-dimensional configuration that increases the distance between the sealring and adjacent components while maintaining a compact planar footprint. This vertical stacking approach resolves the contradiction between miniaturization and reliability.
Solution Approach 2:
The sealring wiring is segmented into multiple separate wiring layers rather than using a single continuous layer. The first sealring wiring and second sealring wiring are formed in different wiring layers and connected through conductive plugs, dividing the sealring function across multiple segments. This segmentation allows for better stress distribution and reduced thermal expansion impact while maintaining the sealring's protective function.
2Reliability
If the sealring wiring width is increased to improve reliability, then crack resistance improves, but the distance to adjacent components decreases and device size increases
Solution Approach 1:
The patent resolves this contradiction by moving the sealring wiring into the third dimension through multi-layer stacking. Instead of increasing the width of a single-layer wiring, the first and second sealring wirings are positioned in different wiring layers with vertical separation. This maintains a small planar distance to adjacent components while providing sufficient physical separation through the vertical dimension, thereby improving crack resistance without increasing device footprint.
Solution Approach 2:
The multi-layer sealring wiring structure embeds one sealring wiring within another in the vertical dimension. The first sealring wiring in one wiring layer is nested with the second sealring wiring in another wiring layer, creating a compact configuration where the sealring functionality is distributed across multiple nested layers. This nesting approach provides enhanced crack resistance through distributed stress while maintaining compact dimensions.
3Reliability
If a multi-layer sealring wiring structure is implemented to increase distance and reduce stress, then reliability improves, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of multiple sealring wirings with the standard multi-layer wiring manufacturing process. The first sealring wiring is formed simultaneously with other wirings in its wiring layer, and the second sealring wiring is formed simultaneously with other wirings in its wiring layer. The conductive plugs connecting them are formed as part of the via formation process. This merging approach integrates the multi-layer sealring structure into existing manufacturing flows, reducing the impact on manufacturing complexity while achieving stress reduction and reliability improvement.
Data Source
AI summary
The reliability of a semiconductor device is improved. Further, miniaturization of the semiconductor device is attained. A sealring is formed in a wiring structure provided over a semiconductor substrate. The sealring has a structure in which sealring wirings respectively formed in a plurality of wiring layers included in the wiring structure are laminated. The position of a side surface on the inner peripheral side of a sealring wiring formed in the wiring layer at the uppermost layer in the wiring layers is located more outside than the position of a side surface on the inner peripheral side of a sealring wiring formed in the wiring layer located one layer lower than the wiring layer at the uppermost layer. The width of the sealring wiring at the uppermost layer is smaller than the width of the sealring wiring located one layer lower than the wiring layer at the uppermost layer.