Seamless Drain-Select Electrodes in 3D Memory via Selective Metal Growth
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Solution Overview
Problem
The formation of seams in drain-select-level electrodes during the etch-back process leads to electrical opens or high-resistivity regions and reliability issues in three-dimensional memory devices due to excessive removal of metallic material and trapped impurities.
Innovation Solution
A method is developed to form seamless drain-select-level electrodes by depositing a metallic material in recess regions around memory stack structures, using thermal migration at a temperature below the melting point to fill inter-pillar gaps without covering the upper portions of the memory pillar structures' sidewalls, ensuring a solid phase metal layer without voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If metallic material is deposited conformally over the entire surface including upper portions of memory pillar structures, then complete coverage is achieved, but seam formation and voids occur during etch-back process
Solution Approach 1:
The patent applies local quality by making the metal-nucleating material selective to specific regions. The material is provided only in the inter-pillar gap region and not on the upper portions of memory pillar structures, creating different material distributions in different locations. This selective placement prevents seam formation during etch-back while ensuring proper electrode formation in the gap regions.
Solution Approach 2:
The patent segments the deposition process into two distinct stages: first depositing metal-nucleating material only in inter-pillar gap regions, then performing a second deposition to form the complete electrode layer. This segmentation allows the first stage to prevent seams while the second stage ensures full coverage, resolving the contradiction between seam-free quality and complete coverage.
2Manufacturing precision
If etch-back process removes excessive metallic material to create seamless electrodes, then seam formation is prevented, but electrical opens and high-resistivity regions occur
Solution Approach 1:
The patent applies preliminary anti-action by pre-placing metal-nucleating material in the inter-pillar gap regions before the main electrode deposition. This preliminary action ensures that metal will be present in critical gap areas after etch-back, counteracting the potential harm of material removal and preventing electrical opens while still allowing seam removal.
Solution Approach 2:
The patent converts the harmful effect of etch-back material removal into a benefit by strategically placing metal-nucleating material in inter-pillar gap regions. The etch-back process that would normally create seams and electrical opens instead creates clean, seamless electrodes because the metal-nucleating material ensures proper metal presence in gap regions after removal of excess material.
3Manufacturing precision
If metal is grown selectively in inter-pillar gap regions only, then seam formation is prevented, but complete electrode coverage is not achieved
Solution Approach 1:
The patent segments the electrode formation into two deposition steps: the first step deposits metal-nucleating material only in inter-pillar gap regions to prevent seams, while the second step deposits additional metal to achieve complete electrode coverage. This segmentation resolves the contradiction by separating the seam-prevention function from the coverage function.
Solution Approach 2:
The patent performs preliminary deposition of metal-nucleating material in inter-pillar gap regions before the main electrode deposition. This preliminary action establishes the seam-free foundation, and the subsequent deposition adds the necessary coverage area, achieving both objectives in sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents seam formation, enhances contact resistance, and increases cell current for vertical field effect transistors, providing a reliable and compact device layout with reduced chip size and simplified fabrication.
Implementation Method 1
inducing thermal migration of the metal at an elevated temperature that is lower than a melting temperature of the metal, wherein the metal is removed from above the top surfaces of the memory pillar structures, and thermally migrated portions of the metal fill a bottom portion of the inter-pillar gap region to provide a drain-select-level electrically conductive layer
Data Source
AI summary
Memory pillar structures extending through an alternating stack of insulating layers and word-line-level electrically conductive layers are formed over a substrate. Each of the memory pillar structures includes a vertical semiconductor channel and a memory film. Each of the memory pillar structures protrudes above an insulating cap layer located above the alternating stack to provide an inter-pillar gap region that laterally extends between laterally-neighboring pairs of the memory pillar structures. A metal-nucleating material having a physically exposed metal-nucleating surface is formed at a bottom of the inter-pillar gap region without covering upper portions of sidewalls of the memory pillar structures. A metal may be selectively grown upward from the physically exposed metal-nucleating surface while suppressing growth of the metal from physically exposed vertical surfaces around the memory pillar structures. A metal layer without a seam may be provided, which may be used for a drain-select-level electrically conductive layer.