Seamless Gap Filling in High Aspect Ratio Semiconductor Structures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor processing methods, such as high density plasma chemical vapor deposition and atomic layer deposition, face challenges in seamlessly filling high aspect ratio gaps and trenches in semiconductor devices, particularly those with aspect ratios greater than 4:1, leading to incomplete filling and seam formation.
Innovation Solution
A method involving the sequential deposition of undoped and doped oxide layers, followed by an annealing process, to form a seamless oxide layer with an interior doped region, which eliminates seams and ensures complete filling of high aspect ratio gaps and trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If HDP CVD or ALD processes are used to fill high aspect ratio gaps, then deposition can be achieved, but seams are formed and complete filling is not achieved
Solution Approach 1:
The gap filling process is segmented into multiple sequential deposition steps: first undoped oxide layer, then doped oxide layer, then second undoped oxide layer. Each layer is deposited separately with controlled thickness and properties, allowing the seam issue to be addressed in the doped layer while maintaining conformal filling in the undoped layers.
Solution Approach 2:
The doped oxide layer acts as an intermediary between the two undoped oxide layers. This intermediate layer has different mechanical and chemical properties that prevent seam formation, while still allowing the overall structure to achieve complete gap filling. The doped layer serves as a mediator that resolves the contradiction between complete filling and seam-free structure.
2Manufacturing precision
If conformal deposition is used for high aspect ratio structures, then thin films can be formed, but adsorption of reactant gases is limited
Solution Approach 1:
The deposition parameters are changed between different layers: undoped oxide layers use standard conformal deposition conditions for high precision, while the doped oxide layer uses modified conditions (different temperature, pressure, or reactant flow rates) to enhance adsorption and deposition rate. This parameter switching allows each layer to be optimized for its specific requirements.
3Reliability
If multiple oxide layers are deposited sequentially, then seamless filling can be achieved, but process complexity increases
Solution Approach 1:
The three separate deposition steps (undoped oxide, doped oxide, undoped oxide) are merged into a single integrated process flow with standardized equipment and procedures. The process uses the same deposition chamber and similar reactants for all layers, combining multiple operations into a unified manufacturing sequence that reduces complexity despite the multiple layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves seamless gap filling and trench isolation, providing reliable insulation and facilitating subsequent processing steps by forming a structurally softer seamless oxide layer that can be easily removed and replaced with a cap oxide layer, ensuring proper protection and planarization.
Implementation Method 1
an annealing process is performed on the second un-doped oxide layer, the doped oxide layer, and the first un-doped oxide to form a seamless oxide layer in the gap
Implementation Method 2
high density plasma chemical vapor deposition (HDP CVD) is used and a directional (bottom-up) CVD process
Implementation Method 3
Adsorption of reactant gases are limited when using ALD and thin, conformal dielectric films with high aspect ratio features may be formed
Data Source
AI summary
A method for seamless gap filling is provided, including providing a semiconductor structure with a device layer having a gap therein, wherein the gap has an aspect ratio greater than 4. A liner layer is formed over the device layer exposed by the gap. A first un-doped oxide layer is formed over the liner layer in the gap. A doped oxide layer is formed over the first undoped oxide layer in the gap. A second un-doped oxide layer is formed over the doped oxide layer in the gap to fill the gap. An annealing process is performed on the second un-doped oxide layer, the doped oxide layer, and the first un-doped oxide to form a seamless oxide layer in the gap, wherein the seamless oxide layer has an interior doped region.