Sequential Equivalence Checking Cutpoint Selection
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Solution Overview
Problem
Sequential equivalence checking of electronic design representations often leads to erroneous declarations of non-equivalence due to clock gating, requiring lengthy and resource-intensive processes to validate equivalence, especially in complex designs with many state elements.
Innovation Solution
A method and system for selecting cutpoints in electronic design representations, executing assume-guarantee proofs, identifying failed assertions, and performing simulations to discard non-equivalent signal pairs, thereby reducing the verification task to smaller, more manageable abstracted representations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential equivalence checking is performed on two representations of an electronic design, then equivalence can be formally proven, but the process requires excessive time and computational resources due to clock gating causing erroneous non-equivalence declarations
Solution Approach 1:
The verification process is segmented into multiple passes: first performing combinational equivalence checking to identify and discard obviously non-equivalent signal pairs, then performing sequential equivalence checking only on the remaining candidate pairs. This segmentation reduces the overall verification time while maintaining accuracy by eliminating obviously non-equivalent pairs before the more time-consuming sequential analysis.
Solution Approach 2:
Combinational equivalence checking is performed as a preliminary action before sequential equivalence checking. This preliminary pass identifies and discards non-equivalent signal pairs that would otherwise consume excessive computational resources during the main sequential verification process, thereby reducing total verification time while preserving reliability.
2Reliability
If sequential equivalence checking is performed on complex designs with many state elements, then comprehensive verification is achieved, but computational resources are excessively consumed
Solution Approach 1:
The verification task is segmented into two distinct phases: combinational equivalence checking followed by sequential equivalence checking. This segmentation divides the computational workload, allowing the system to use less computational resources overall while maintaining verification completeness by systematically addressing different aspects of equivalence in sequence.
Solution Approach 2:
Non-equivalent signal pairs are extracted and discarded from the verification set during the combinational equivalence checking phase. By removing these obviously non-equivalent pairs before proceeding to sequential verification, the computational resources required for the main verification task are significantly reduced while maintaining comprehensive verification of the remaining candidate pairs.
3Loss of energy
If clock gating is used in electronic design to reduce power consumption, then power efficiency is improved, but equivalence checking accuracy deteriorates due to erroneous non-equivalence declarations
Solution Approach 1:
Combinational equivalence checking is performed as a preliminary action that correctly handles clock gating scenarios by analyzing the combinational logic paths. This preliminary pass identifies signal pairs that are truly equivalent despite clock gating, preventing erroneous non-equivalence declarations in the subsequent sequential verification phase and maintaining equivalence checking accuracy while preserving the power-saving benefits of clock gating.
Data Source
AI summary
A method for sequential equivalence checking (SEC) of two representations of an electronic design includes selecting by a processor a plurality of cutpoints in the two representations of the electronic design, rendering the two representations of the electronic design abstracted; executing by the processor an assume-guarantee (AG) proof on the two abstracted representations of the electronic design; identifying by the processor a failed assertion indicating non-equivalence of a signal pair relating to one of the cutpoints; and performing by the processor a simulation on the two representations of the electronic design by successively inputting input stimuli of a trace corresponding to the failed assertion in a sequential order in which the input stimuli appear in the trace at inputs of the two representations of the electronic design to identify whether there is one or a plurality of additional non-equivalent signal pairs relating to other cutpoints of said plurality of cutpoints.