SEC Parity Check Matrix Layout to Minimize DRAM Aliasing Errors
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Solution Overview
Problem
In semiconductor memory devices, single error correction (SEC) codes often result in aliasing errors due to false corrections, leading to increased error detection and data damage, particularly in Dynamic Random Access Memory (DRAM) devices, where the high probability of aliasing errors increases with the number of check bits.
Innovation Solution
A system and method for generating a minimal aliasing error correction code using a parity check matrix with distinct nonzero binary column vectors, where the check submatrix is reversible and an identity matrix, to reduce the occurrence of aliasing errors in SEC codes applied to DRAM devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single error correction (SEC) code is applied to DRAM devices, then error correction capability is improved, but aliasing errors increase due to false corrections
Solution Approach 1:
The patent changes the structural parameters of the parity check matrix H by imposing specific constraints: all column vectors must be nonzero and mutually distinct. This parameter change in the matrix structure fundamentally alters the error correction behavior, reducing false corrections and aliasing errors while maintaining SEC capability.
Solution Approach 2:
The patent applies local quality by making each column vector of the parity check matrix have unique properties (nonzero and distinct). This local distinction in column vector characteristics ensures that each bit position contributes uniquely to error detection, preventing the aliasing that occurs when column vectors are identical or zero.
2Measurement precision
If the number of check bits is increased in SEC code, then error detection capability is improved, but the probability of aliasing errors increases
Solution Approach 1:
The patent changes the relationship between check bits and aliasing by enforcing that all column vectors in H are nonzero and distinct. This parameter constraint ensures that increasing check bits (increasing r) expands the space of unique column vectors available, which actually reduces aliasing probability rather than increasing it, as each additional check bit provides more unique syndromes.
3Reliability
If a parity check matrix with more check bits is used, then code strength is improved, but the number of operations increases
Solution Approach 1:
The patent applies partial action by imposing only the necessary constraints on the parity check matrix (nonzero and distinct column vectors) rather than requiring full optimization. This partial constraint approach achieves sufficient error correction with minimal operational overhead, avoiding excessive computation while maintaining code strength.
Data Source
AI summary
Disclosed is a method and system for providing a minimal aliasing error correction code. In constructing a single error correction (SEC) code by constructing a parity check matrix H for a data length k applied to a device, as the SEC code is designed to be valid and minimize generation of aliasing by checking some bits rather than all bits when nonzero binary column matrices different from each other are arranged in the parity check matrix, destruction of information can be prevented, and reliability of a device applying the SEC, such as DRAM or the like, can be improved.