Second-Order CIC Filter Layout for Smaller ADC Die Area
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Solution Overview
Problem
Existing cascaded integrator comb (CIC) filters, particularly Hogenauer's design, occupy a significant percentage of the die area in integrated circuits without providing any functional advantage.
Innovation Solution
Implementing a CIC filter using a novel electronic configuration based on the transfer function equation c(k) = k + 1 for k < OSR and c(k) = 2*OSR - 1 - k for k >= OSR, with counter signals incrementing from zero to 2*OSR - 2, and utilizing a counter modifier circuit to derive alternate counter signals for sub-filters, reducing die size by half.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If Hogenauer's CIC filter implementation is used, then the filter provides complete functionality, but the die area occupied is significant
Solution Approach 1:
The filter is divided into multiple sub-filters (first sub-filter, second sub-filter, etc.), each handling a portion of the filtering function. This segmentation allows the overall filter to be implemented with reduced die area by distributing the computational load across simpler, parallel sub-units rather than a single complex structure.
Solution Approach 2:
The invention changes the mathematical parameters and equations used in the filter implementation. Specifically, it employs alternative equations for calculating filter coefficients and uses a modified counter signal approach (incrementing from zero to 2*OSR-2) that reduces the computational resources required, thereby reducing die area while maintaining functionality.
2Area of stationary object
If die size is reduced, then area efficiency improves, but filter functionality may be compromised
Solution Approach 1:
Multiple sub-filters are combined through a combining circuit to produce the final filtered output. This merging approach ensures that the reduced-area sub-filters collectively provide the complete filtering functionality of the original design, maintaining reliability while achieving area reduction.
Solution Approach 2:
The counter modifier circuit and coefficient calculation circuits are designed to serve multiple sub-filters simultaneously, providing universal functionality across different filter stages. This multi-functionality allows the same hardware resources to be reused across multiple sub-filters, ensuring complete filtering functionality is achieved without proportionally increasing die area.
Data Source
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AI summary
An electronic filter comprising: a first coefficient circuit (220) to provide a first coefficient-signal (coeff0) by applying coeff0=2*OSR-1-counter0, where OSR is the oversampling ratio, when a first counter-signal (counter0)>=OSR and applying coeff0=counter0+1, when counter0<0SR. The filter also comprises a first summation circuit (230) to provide a first polarity-signal, polarity0, as either: coeff0 if the ADC bitstream signal is positive; or -coeff0 if the ADC bitstream signal is negative; and integrate polarity0. The filter also comprises a counter modifier circuit (280) to provide a second counter-signal, derived from counter0; a second coefficient circuit (260) to provide a second coefficient-signal; and a second summation circuit (270) to provide a second sub-filter signal. The filter also comprises an output logic circuit (290) to provide a filter output signal to the filter output terminal (213), by switching between providing the first sub-filter signal and the second sub-filter signal as the filter output signal, at the frequency of a clock-signal.