Second Word Line and Y-Mux Layout for Low-Power OTP Programming
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Solution Overview
Problem
Existing memory cell programming methods in eFuse or one-time-programming (OTP) memories incur high active power due to the assertion of all second word lines (SWLs) in parallel with word lines (WLs) during programming cycles, which is inefficient and energy-consuming.
Innovation Solution
The proposed solution involves coupling second word lines (SWLs) in parallel with bit lines (BLs instead of WLs, using low threshold voltage (LVT) devices, and incorporating SWLs and BLs into a shared decoder, reducing capacitive loading and active power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all second word lines (SWLs) are asserted in parallel with word lines (WLs) during programming cycles, then stacked access transistors are protected from over-voltage stress, but active power consumption increases
Solution Approach 1:
The patent applies local quality by differentiating the treatment of selected versus unselected memory columns. Instead of uniformly asserting all SWLs, the invention selectively activates SWLs only for unselected columns while leaving them inactive for selected columns. This localized approach maintains over-voltage protection where needed (unselected columns) while avoiding unnecessary power consumption in selected columns, directly resolving the contradiction between reliability and energy usage.
2Reliability
If second word lines (SWLs) are coupled in parallel with word lines (WLs), then stacked access transistors are protected, but capacitive loading increases
Solution Approach 1:
The patent segments the SWL network into column-specific control lines rather than a single parallel assertion mechanism. Each SWL is independently controlled based on column selection signals, allowing the system to divide the protective function into discrete, manageable segments. This segmentation reduces the simultaneous capacitive burden compared to asserting all SWLs in parallel, while maintaining protection for unselected columns.
3Reliability
If all second word lines (SWLs) are activated in every programming cycle, then unselected stacked access transistors are protected, but programming efficiency decreases
Solution Approach 1:
The patent introduces dynamic control of SWL activation based on real-time programming cycle requirements. Rather than static activation of all SWLs, the system dynamically enables or disables specific SWLs according to which columns are selected for programming. This dynamic approach maintains necessary protection while reducing redundant activations, thereby improving programming efficiency without sacrificing reliability.
Data Source
AI summary
A memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines, each of the word lines coupled to a corresponding row of the memory cells; a plurality of bit lines, each of the bit lines coupled to a corresponding column of the memory cells; and a plurality of second word lines, each of the second word lines coupled to a corresponding column of the memory cells. Each of the memory cells comprises: a first metal-oxide-semiconductor (MOS) transistor coupled to a corresponding word line; a second MOS transistor coupled to the first MOS transistor and a corresponding second word line; a memory element coupled to the second MOS transistor; and a third MOS transistor coupled to the memory element and a corresponding bit line.