Digital Signal Processing with Secondary Accumulator Down-Sampling
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Solution Overview
Problem
Conventional signal processing methods for digital musical tone signals face high processing loads during down-sampling, which limits the capacity for other processing and requires frequent data evacuation from the accumulator to memory, leading to inefficient use of digital signal processors.
Innovation Solution
A signal processing method and device that distributes high processing loads across multiple periods, using a secondary accumulator register to store intermediate results, allowing other processing to occur during interruptions and eliminating the need for data evacuation to memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If high processing load steps are concentrated per 1 fs, then down-sampling processing is simplified without complex distributed processing, but the processing capacity per fs is reduced and other processing cannot be performed
Solution Approach 1:
The patent segments the high processing load steps into multiple periods (e.g., distributing 200 steps across 6 fs instead of concentrating in 1 fs). This segmentation allows the processing load to be spread out, enabling other processing to occur during intervals while maintaining overall processing capability and simplicity.
2Reliability
If intermediate results are stored in accumulator and evacuated to memory, then data can be preserved for later use, but additional steps and specific hardware paths are required
Solution Approach 1:
The patent merges the accumulator function with the memory function by allowing the accumulator to directly hold intermediate results throughout multiple periods without evacuation to separate memory. This combining eliminates the need for separate memory evacuation paths and reduces hardware complexity while maintaining data preservation capability.
3Manufacturing precision
If 200 steps are performed per fs, then down-sampling is achieved, but the processing load is high and reduces steps available for other processing
Solution Approach 1:
The patent implements periodic action by distributing the 200 down-sampling steps across multiple periods (e.g., 6 fs) rather than executing them all in one period. This periodic distribution maintains the required down-sampling accuracy while reducing the processing load per period, thereby increasing overall processing throughput and enabling additional processing during intervals.
Data Source
AI summary
Periodically sampled digital data (e.g., digital audio data) are once stored in a work RAM and are then subjected to signal processing such as arithmetic operations using coefficients. A primary accumulator register stores results of arithmetic operations. A secondary accumulator register is specialized in handling a relatively high processing load (e.g., down-sampling) having a plurality of steps, which are distributed and appropriately assigned to a plurality of periods in response to output timings. In order to execute other processing in each period, intermediate results of arithmetic operations regarding the relatively high processing load are temporarily stored in the secondary accumulator register. The number of steps assigned to each period is appropriately changed in response to interruption of the other processing, whereas the relatively high processing load is given a first priority in comparison with the other processing.