Secondary Counter Storage Reduces On-Chip Memory in Flow Tables
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Solution Overview
Problem
Networking devices face challenges in maintaining accurate packet and byte counters while minimizing on-chip storage, power consumption, and CPU burden, especially when dealing with large numbers of counters that require frequent updates and long-term accumulation without counter overflow.
Innovation Solution
The implementation of a secondary counter storage system that uses a content addressable memory (CAM) to manage overflow conditions by incrementing an overflow count value and consolidating counter values from a primary flow-counter bank to secondary storage, reducing the need for extensive on-chip memory and maintaining accurate counts over time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large numbers of counters are implemented on-chip to maintain accurate packet and byte counts, then counter accuracy and reliability are improved, but on-chip storage requirements and chip area increase significantly
Solution Approach 1:
The counter storage is segmented into two parts: a smaller on-chip counter bank for active counters and a larger off-chip secondary storage for accumulated counters. This segmentation allows the system to maintain accurate counters for currently active flows on-chip while storing historical counter data off-chip, thus reducing on-chip storage requirements while preserving counter accuracy.
Solution Approach 2:
The patent extracts the secondary storage function from the on-chip counter bank and places it in off-chip memory. The counter management system periodically reads counters from the on-chip bank, accumulates them in secondary storage, and clears the on-chip counters. This extraction reduces on-chip storage requirements while maintaining reliable counter tracking.
2Adaptability or versatility
If the number of counters is increased to support more routes and traffic categories, then monitoring capability and versatility are improved, but the frequency at which software can read individual counters decreases
Solution Approach 1:
The counter reading process is segmented into periodic batch operations rather than individual real-time reads. The system periodically reads groups of counters from the on-chip bank to secondary storage, allowing software to maintain high monitoring capability for many routes while accepting periodic updates rather than continuous real-time access to each counter.
3Reliability
If full counters are stored directly on the packet switching chip, then counter accuracy is maintained, but manufacturing cost and device complexity increase
Solution Approach 1:
The counter storage architecture is segmented into on-chip and off-chip components. The on-chip portion stores only active counter values, while off-chip memory stores accumulated historical data. This segmentation reduces the total on-chip memory required, lowering manufacturing costs while maintaining counter accuracy through periodic synchronization.
Solution Approach 2:
The patent extracts the bulk counter storage function from the chip to off-chip memory, keeping only the essential active counter storage on-chip. This extraction reduces chip complexity and manufacturing cost while maintaining counter accuracy through the periodic read-accumulate-clear cycle.
4Use of energy by stationary object
If on-chip counter storage is reduced to lower cost and power consumption, then manufacturing cost and power usage are improved, but the system must ensure counters do not wrap
Solution Approach 1:
The patent extracts the counter accumulation function to off-chip secondary storage, allowing the on-chip counters to be smaller and reset periodically. The secondary storage maintains the accumulated count to prevent wrapping, while the on-chip counters only need to store temporary values until the next accumulation cycle.
Solution Approach 2:
The system performs preliminary accumulation of counter values in secondary storage before the on-chip counters need to wrap. By periodically reading and accumulating counter values before they overflow, the system prevents wrap-around errors while allowing smaller on-chip counter storage.
Data Source
AI summary
In one embodiment, a CAM overflow structure holds flow indices in a CAM and each CAM entry is associated with an overflow count value (OCV) entry holding an OCV. If counter in a primary flow-counter bank (PFCB) overflows when updated, the CAM is searched and, if the index of the counter that overflowed is stored in the associated OCV entry, the OCV is incremented. The counter values in the PFCB are scanned according to specified criteria and transferred to a secondary flow-counter bank (SFCB) held in non-custom system RAM. When a counter value is transferred to the SFCB the corresponding OCV is appended to the counter value.