Secondary CPU Soft Reboot via Software Mailbox Control
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Solution Overview
Problem
Current multi-processor systems, such as ARM64 platforms, rely on hardware or firmware for secondary CPU initialization, which limits flexibility and efficiency in system reboot processes, particularly in scenarios where hardware control is not available.
Innovation Solution
The system software allocates physical memory frames as 'mailboxes' for secondary CPUs, causing them to repark in a code loop that checks for changes in a jump address slot, allowing the system software to write a physical address for boot code, enabling soft rebooting without hardware or firmware control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware or firmware-coordinated protocol is used for secondary CPU initialization, then system reliability is improved, but device complexity and reliance on external controls increase
Solution Approach 1:
The patent implements self-service by enabling secondary CPUs to autonomously monitor and detect changes in the jump address slot through their own execution threads, eliminating the need for external hardware or firmware coordination. The CPUs independently check the mailbox memory location and execute the boot code address when changed, achieving self-initialization without external control mechanisms.
Solution Approach 2:
The patent extracts the initialization control function from hardware/firmware layers and transfers it to the software layer. By removing the dependency on hardware-coordinated protocols and firmware calls, the system achieves software-controlled CPU initialization, reducing device complexity while maintaining reliability through software-based coordination.
2Manufacturing precision
If hardware or firmware control is used for CPU state coordination, then initialization accuracy is improved, but adaptability to different platforms decreases
Solution Approach 1:
The patent implements universality by creating a platform-agnostic software-based initialization mechanism that works across different CPU architectures and firmware environments. The mailbox-based approach with jump address slots can be implemented on any platform with memory access capabilities, making the system adaptable to various hardware configurations without requiring architecture-specific hardware protocols.
Solution Approach 2:
The patent substitutes mechanical/hardware control mechanisms with software-based control. Instead of relying on hardware-coordinated protocols or firmware calls that are tightly coupled to specific architectures, the system uses software-managed memory locations (mailboxes) and conditional jumps, which can be implemented universally across different platforms while maintaining precise initialization control.
3Adaptability or versatility
If mailbox approach with code loops is used for secondary CPU initialization, then adaptability is improved, but productivity during soft reboot decreases
Solution Approach 1:
The patent applies preliminary action by having secondary CPUs pre-position themselves in waiting loops at designated mailbox memory locations before the soft reboot occurs. When the primary CPU needs to initialize a secondary CPU, it simply writes the boot code address to the pre-configured mailbox location, and the waiting CPU detects the change and executes. This eliminates the need for complex initialization sequences during reboot, significantly improving productivity while maintaining adaptability.
Data Source
AI summary
A method of initializing a secondary processor pursuant to a soft reboot of system software comprises storing code to be executed by the secondary processor in memory, building first page tables to map the code into a first address space and second page tables to identically map the code into a second address space, fetching a first instruction of the code based on a first virtual address in the first address space and the first page tables, and executing the code beginning with the first instruction to switch from the first to the second page tables. The method further comprises, fetching a next instruction of the code using a second virtual address, which is identically mapped to a corresponding machine address, turning off a memory management unit of the secondary processor, and executing a waiting loop until a predetermined location in the physical memory changes in value.