Secondary Polysilicon Structures for Dense Semiconductor Isolation
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Solution Overview
Problem
As semiconductor devices shrink in size, maintaining physical alignment and electrical isolation of successive layers becomes challenging, and there is a need to reduce the complexity and size of gate structures and multilayer interconnects to improve device density, cycle time, and yield.
Innovation Solution
The introduction of secondary polysilicon structures formed over isolation structures within IC devices, which improve uniformity and allow for additional conductive features like vias, power rails, and heat sinks, reducing the need for additional conductive elements and increasing device density without increasing height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor devices are shrunk in size to increase device density, then device density improves, but maintaining physical alignment and electrical isolation of successive layers becomes difficult
Solution Approach 1:
The patent introduces a third-dimensional structure by forming protruding portions that extend upward from the substrate surface. These protruding portions carry conductive layers and interconnect structures above the plane of the substrate, allowing vertical stacking of interconnect layers. This dimensional transition from 2D planar layout to 3D vertical stacking enables higher device density while maintaining adequate spacing and isolation between conductive elements through the vertical dimension.
2Adaptability or versatility
If additional conductive elements are added to improve device functionality, then device functionality improves, but device complexity and size increase
Solution Approach 1:
The protruding portions serve multiple functions: they provide mechanical support for overhanging conductive layers, act as isolation structures between adjacent conductive elements, serve as anchors for vias and contacts, and enable routing of interconnect lines. By making these protruding portions multi-functional, the patent reduces the need for separate dedicated structures for each function, thereby decreasing overall device complexity while maintaining enhanced functionality.
3Adaptability or versatility
If additional conductive elements are added to improve device functionality, then device functionality improves, but device size increases
Solution Approach 1:
The patent utilizes vertical stacking to place conductive layers, vias, and interconnect structures in the third dimension above the substrate surface. The protruding portions extend upward to support these elevated conductive elements. This vertical arrangement allows multiple conductive elements to be packed into a smaller footprint area on the substrate, thereby improving device functionality without proportionally increasing the device's planar size.
Data Source
AI summary
Disclosed are methods of manufacturing semiconductor devices that include the operations of forming an isolation structure in a semiconductor substrate, forming an active region adjacent the isolation structure, forming at least two primary polysilicon structures over the active region, the primary polysilicon structures defining a contacted polysilicon pitch (CPP), and forming a secondary polysilicon structure over the isolation structure. In some methods, the secondary polysilicon structure is further modified and/or replaced in order to provide additional functional elements on the semiconductor devices.