Secondary Processor Secure Data Access via MMU Translation

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Solution Overview

Problem

In data processing apparatuses with a primary and secondary processor, extending secure and non-secure domains to the secondary processor is challenging due to security vulnerabilities and the need for a suitable operating system, making it difficult to perform both secure and non-secure data processing operations reliably.

Innovation Solution

The secondary processor is configured to perform both secure and non-secure data processing operations with a memory management unit that translates virtual memory addresses to physical addresses based on a page table base address defined by the primary processor, preventing access to secure data by non-secure operations and maintaining security by controlling access through hardware mechanisms.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the secondary processor is given access to secure data to perform secure data processing operations, then the functionality and productivity of the secondary processor is improved, but the security of the data processing apparatus is compromised

Engineering Contradiction:

Improvefunctionality of secondary processorVSAvoidsecurity of data processing apparatus

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The memory space is segmented into secure and non-secure regions, with the MMU enforcing access controls that allow the secondary processor to access only non-secure data and specific secure data through controlled mechanisms, preventing unauthorized access while maintaining functionality

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The memory management unit acts as an intermediary between the secondary processor and memory, translating virtual addresses to physical addresses and enforcing access permissions, thereby enabling the secondary processor to perform secure operations without direct access to secure data

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If the secure domain is extended to encompass elements of the secondary processor, then the secondary processor can perform secure operations, but the reliability of the security setup is reduced

Engineering Contradiction:

Improveability of secondary processor to perform secure operationsVSAvoidreliability of security setup

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

Instead of extending the secure domain globally to include the secondary processor, the system applies local quality control by allowing the secondary processor to access specific secure data regions through controlled mechanisms while maintaining the integrity of the overall secure domain

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The MMU creates a virtual address space for the secondary processor that copies or maps only the necessary secure data regions, allowing secure operations without giving the secondary processor direct access to the entire secure domain

Inventive Principle:

Principle #26Copying

3Reliability

If an operating system is implemented on the secondary processor to support secure and non-secure domains, then the secondary processor can reliably perform both types of operations, but the device complexity increases

Engineering Contradiction:

Improveability to perform secure and non-secure operationsVSAvoidcomplexity of secondary processor configuration

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The MMU is designed to handle both secure and non-secure address translations using a unified mechanism with a single page table base address, eliminating the need for separate operating system implementations for different security domains while maintaining reliability

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8959304B2Management of data processing security in a secondary processor

Publication Date: 2015.02.17 ARM LTD

AI summary

A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory configured to store secure data used by the secondary processor when performing the secure data processing operations and configured to store non-secure data used by the secondary processor when performing the non-secure data processing operations, wherein the secure data cannot be accessed by the non-secure data processing operations, wherein the secondary processor comprises a memory management unit configured to administer accesses to the memory from the secondary processor, the memory management unit configured to perform translations between virtual memory addresses used by the secondary processor and physical memory addresses used by the memory, wherein the translations are configured in dependence on a page table base address, the page table base address identifying a storage location in the memory of a set of descriptors defining the translations, wherein the page table base address is defined by the primary processor and cannot be amended by the secondary processor.