Floating-Gate Secret Storage With Time-Limited Charge Retention

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Solution Overview

Problem

Current memory structures, particularly non-volatile ones like flash memory, persistently store secrets such as encryption keys, making them vulnerable to reverse engineering when powered off, and battery-backed solutions drain energy and are susceptible to attacks.

Innovation Solution

A semi-volatile memory structure is designed with modified floating gate memory cells that intentionally leak charge over time, setting an expiration date for stored data, rendering it inaccessible after a predetermined period, thus hindering reverse engineering and conserving energy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of stationary object

If non-volatile memory structures are used to store secrets, then data persistence is improved, but security against reverse engineering deteriorates

Engineering Contradiction:
Improvedata persistenceVSAvoidreverse engineering vulnerability
Core Design Contradiction:
Duration of action of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent applies parameter changes by modifying the retention time parameter of the memory cell to create a time-dependent security mechanism. The memory cell is designed with a specific retention time that causes automatic data erasure after a predetermined period, transforming the static persistence characteristic into a dynamic one that degrades over time, thereby preventing long-term secret extraction while maintaining short-term data availability.

Inventive Principle:
Principle #35Parameter changes

2Duration of action of stationary object

If battery-backed memory is used to extend data retention, then data persistence is improved, but energy consumption increases

Engineering Contradiction:
Improvedata retention timeVSAvoidbattery energy consumption
Core Design Contradiction:
Duration of action of stationary objectVSUse of energy by moving object

Solution Approach 1:

The patent implements self-service by designing the memory cell to automatically manage its own data retention and erasure without requiring external power management. The memory structure inherently provides the desired retention time through its physical characteristics, eliminating the need for continuous battery power or active refresh circuits, thus achieving energy-free extended retention.

Inventive Principle:
Principle #25Self-service

3Reliability

If non-volatile memory is used for secret storage, then data availability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvedata availabilityVSAvoidmemory structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the complexity of power management and data erasure logic from the overall system by embedding these functions directly into the physical structure of the memory cell itself. The retention time is determined by inherent physical parameters of the memory structure rather than requiring external control circuits, thereby simplifying the overall device architecture while maintaining reliable time-limited data availability.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach adds complexity to reverse engineering, provides defense-in-depth, and conserves energy by making data self-erase after a set time, reducing the risk of secret extraction during device off periods and extending battery life.

Implementation Method 1

The memory cell may be selected or tuned such that the actual retention time of the memory cell will fall within a window surrounding the desired retention time. In some cases, the retention time may be on the order of days, weeks, or months... the floating gate memory cell that is similar to structures currently used in flash memory; however, the floating gate memory cell used in embodiments herein may be manufactured using modified parameters (e.g., oxide composition, quality, thickness, aging, etc.) that create a leaky gate oxide so that the charge stored in the floating gate (or sidewall oxide for sidewall storage-based memory cells) purposely leaks over time.

Methodology Applied
Scientific EffectOxide leakage:

Data Source

PatentUS11984512B2Memory structure for self-erasing secret storage
Publication Date: 2024.05.14 SK HYNIX NAND PRODUCT SOLUTIONS CORP
  • US11984512B2 patent drawing
  • US11984512B2 patent drawing
  • US11984512B2 patent drawing

AI summary

In one embodiment, memory cell includes a control gate, a floating gate, a substrate comprising a source region and a drain region, a first isolator between the control gate and floating gate, and a second isolator between the floating gate and the substrate. The memory cell is configured to have a retention time that is within a statistical window around a selected lifespan. The selected lifespan may be less than ten years, such as, for example, less than one year, less than one month, or less than one week.