Section-Based Compiler Feedback for CGRA Mapping Failures

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Solution Overview

Problem

Compiling compute graphs for coarse-grained reconfigurable architectures (CGRAs) remains a challenge due to the need for efficient mapping of operations to processor instructions in both space and time, particularly for parallel and pipelined execution of massively parallel computations required by machine learning and artificial intelligence programs.

Innovation Solution

A compiler system with multiple levels that can detect and handle errors during compilation, allowing iterative feedback to adjust the compilation process, ensuring effective mapping of high-level programs to reconfigurable dataflow processors (RDPs) with arrays of configurable units.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single-level compiler is used for compiling compute graphs to CGRAs, then the device complexity is reduced, but the manufacturing precision and mapping accuracy of operations to processor instructions deteriorates

Engineering Contradiction:

Improvecompiler structure complexityVSAvoidoperation mapping accuracy

Core Design Contradiction:

Device complexityVSManufacturing precision

Solution Approach 1:

The compiler is divided into multiple levels (first compiler level, second compiler level, third compiler level) that perform different stages of compilation. Each level handles specific aspects of the compilation process, allowing for specialized optimization at each stage while maintaining overall system manageability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical dimension to the compiler architecture, organizing compilation tasks across multiple levels rather than a single flat level. This dimensional organization allows complex compilation tasks to be distributed across levels with different levels of abstraction and specialization.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If multiple compiler levels are implemented to improve mapping accuracy, then the manufacturing precision improves, but the device complexity increases

Engineering Contradiction:

Improveoperation mapping accuracyVSAvoidcompiler structure complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The second compiler level receives feedback information about mapping failures and uses this feedback to generate error handling data that is returned to the first compiler level. This feedback mechanism enables iterative improvement of the mapping process, allowing the system to learn from failures and improve future mapping attempts.

Inventive Principle:

Principle #23Feedback

3Reliability

If iterative feedback is implemented to handle compilation errors, then the reliability improves, but the loss of time increases due to repeated compilation passes

Engineering Contradiction:

Improvecompilation success rateVSAvoidcompilation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The system performs preliminary analysis and error detection at the second compiler level before finalizing the compilation. By identifying and addressing potential issues early in the process, the system can prevent time-consuming rework later and reduce the overall number of iteration cycles needed.

Inventive Principle:

Principle #10Preliminary action

4Productivity

If coarse-grained reconfigurable architectures are used to enable parallel execution, then the productivity improves, but the device complexity increases

Engineering Contradiction:

Improveparallel computation throughputVSAvoidprocessor architecture complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent employs multiple intermediate representations (first intermediate representation, second intermediate representation, third intermediate representation) that transform the computation graph through different parameter configurations and abstractions at each compilation level, enabling optimization for the target CGRA architecture.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20250265053A1Section-Based Iterative Feedback to Different Levels of Compiler

Publication Date: 2025.08.21 SAMBANOVA SYSTEMS INC

AI summary

Systems and methods are disclosed for transforming a high-level program of a computing task into configuration data executable by a reconfigurable dataflow processor (RDP) including one or more arrays of configurable units where the compiler may include a first, second and third compiler levels. The third compiler level may receive a first intermediate representation (IR) of the high-level program generated by the second compiler level where the first IR is based on a second IR generated by the first compiler level. The third compiler level may determine a failure occurred during generating of the configuration data based on the first IR, determine, based on the failure and error handling data for the failure, whether to return compilation operations to one of the first compiler level or the second compiler level and return the compilation operations to the determined one of the first compiler level and the second compiler level.