Sectional Transistor Layout for Higher Current and Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional semiconductor transistor devices have limitations in achieving high performance and efficiency due to restricted current flow and increased parasitic interconnection capacitance, which hinders their ability to operate at high speeds and reduce size effectively.
Innovation Solution
The implementation of sectional transistor devices with multiple sections connected by interconnection wiring layers, including metal-0, intermediate Li1, and metal-1 layers, allows for increased channel count without increasing interconnects, reducing parasitic capacitance and enabling higher operating speeds or smaller device sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional transistor devices are used with single-channel layout, then device size is reduced, but current flow capacity is restricted and operating speed decreases
Solution Approach 1:
The transistor device is divided into multiple sections (first section, second section, third section) with each section containing channels arranged in different orientations. This segmentation allows current to flow through multiple parallel paths, increasing total current capacity while maintaining a compact footprint. The sections are interconnected through shared source and drain regions, enabling efficient current distribution without requiring proportionally larger device area.
2Productivity
If more interconnection wiring layers are added to increase channel count, then current capacity improves, but parasitic interconnection capacitance increases
Solution Approach 1:
Multiple channels are merged into a single integrated structure by sharing common source and drain regions across different sections. Instead of using separate interconnection wiring layers for each channel, the invention combines channels through shared regions, thereby increasing channel count while minimizing the number of discrete interconnections. This merging approach significantly reduces parasitic interconnection capacitance compared to conventional multi-layer interconnect structures.
Data Source
AI summary
A semiconductor device including a substrate; a first active region disposed in the substrate, the first active region having one or more first type channels and a first plurality of doped regions; a second active region disposed in the substrate, the second active region having one or more second type channels and a second plurality of doped regions, the second active region being physically separated from the first active region by a STI region; an intermediate wiring layer disposed above the substrate, the intermediate wiring layer having a plurality of fingers connected to the first plurality of doped regions and the second plurality of doped regions, respectively; and a metal wiring layer having a source finger and a drain finger, wherein the source finger is connected to a first group of the plurality of fingers, and the drain finger is connected to a second group of the plurality of fingers.