Sectioned Bit Line SRAM for Reduced Capacitance
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Solution Overview
Problem
Conventional SRAMs face challenges in achieving smaller bit line capacitance and higher density memory arrays due to limitations in reducing bit line capacitance, which affects memory cell sensing speed and stability, and existing DRAM structures are restricted by limited memory cell selection and bit line configurations.
Innovation Solution
The implementation of sectioned bit lines (SBLs) in SRAMs, where each SBL is connected to a global bit line and can be pre-charged to high, allowing for improved memory cell stability and reduced bit line capacitance through the use of pass gates that act as conductors and isolators, enabling efficient data transfer and reduced overall bit line length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to shorten bit line, then bit line capacitance is reduced, but memory cell active current is also reduced
Solution Approach 1:
The bit line is divided into multiple sections, each serving a specific function. Local bit lines connect to individual memory cells, while global bit lines collect signals from multiple local bit lines. This segmentation allows the bit line structure to be optimized independently in different regions, enabling capacitance reduction without proportionally reducing memory cell active current.
2Speed
If the number of memory cells per bit line is reduced to improve sensing speed, then bit line capacitance is reduced, but memory array density is reduced
Solution Approach 1:
The memory array is organized into multiple banks, each with its own local bit lines that connect to a shared global bit line. This allows parallel operation of multiple memory cells across different banks, maintaining high memory array density while keeping the effective bit line capacitance low for fast sensing operations.
Solution Approach 2:
The patent introduces a hierarchical bit line structure with local and global levels, adding a dimensional aspect to the bit line organization. Instead of a single flat bit line connecting all memory cells, the system uses local bit lines for individual cell access and global bit lines for signal aggregation, effectively distributing the sensing load across multiple dimensions.
3Quantity of substance
If pass gates are used to connect local bit lines to global bit lines, then bit line capacitance is reduced, but device complexity increases
Solution Approach 1:
The pass gates are designed with dual functionality: they serve as selection switches for individual memory cells and as isolation elements that control signal flow between local and global bit lines. This multi-functionality reduces the need for separate components, thereby limiting the increase in device complexity while achieving capacitance reduction.
Data Source
AI summary
A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described. In one illustrative implementation, the sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. In other implementations, an SRAM memory device may be configured involving sectioned bit lines and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.