Sectioned Extension Regions in Field-Effect Transistors
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Solution Overview
Problem
Current field-effect transistor structures face challenges in improving the figure of merit, particularly as device size increases, where increased OFF-state capacitance and decreased ON-state resistance result in a constant product, which is not effectively enhanced by historical approaches such as strain engineering, gate oxide scaling, or different geometries.
Innovation Solution
A field-effect transistor structure is developed with a gate structure over a channel region, featuring spaced-apart sections of an extension region that overlap with source/drain regions, allowing for a modulated doping profile and reduced OFF-state capacitance without requiring strain engineering or gate oxide scaling, and incorporating a method of forming these sections through masked ion implantation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is increased, then OFF-state capacitance increases, but ON-state resistance decreases
Solution Approach 1:
The extension region is divided into multiple sections (first section, second section, etc.) that are spaced apart along the longitudinal axis of the gate structure. This segmentation allows the extension region to overlap with source/drain regions while maintaining gaps that reduce capacitance coupling, thereby lowering OFF-state capacitance without sacrificing the beneficial effects of the extension region on carrier flow and ON-state resistance
Solution Approach 2:
The extension region is positioned specifically in the lightly-doped drift region adjacent to the drain, with sections spaced to provide localized doping enhancement where needed. This creates non-uniform doping distribution that optimizes carrier concentration in critical areas while maintaining lower capacitance in other regions, improving the figure of merit
2Reliability
If historical approaches (strain engineering, gate oxide scaling, different geometries) are used, then carrier mobility or device performance is improved, but device complexity increases
Solution Approach 1:
The invention changes the doping parameter by introducing a sectioned extension region with specific doping concentrations in the drift region. This modifies the electrical characteristics and carrier mobility through doping profile optimization rather than through structural changes like strain engineering or geometry modification, thereby improving performance without increasing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly improves the figure of merit by reducing OFF-state capacitance, enhancing performance without altering device geometry or using strain engineering, and allows for efficient carrier flow management.
Implementation Method 1
incorporating a method of forming these sections through masked ion implantation
Data Source
AI summary
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is formed over a channel region of a substrate. A first source/drain region is positioned in the substrate adjacent to a first sidewall of the gate structure, a second source/drain region is positioned in the substrate adjacent to a second sidewall of the gate structure, and an extension region is positioned in the substrate. The extension region includes first and second sections that each overlap with the first source/drain region. The first and second sections of the extension region are spaced apart along a longitudinal axis of the gate structure. A portion of the channel region is positioned along the longitudinal axis of the gate structure between the first and second sections of the extension region.