QC-LDPC Bit Interleaving by Sectioned Constellation Mapping
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Solution Overview
Problem
Existing bit-interleaved coding and modulation systems with quasi-cyclic low-density parity-check codes face inefficiencies in interleaving, leading to impaired parallelism and limited bit interleaver configurations, particularly when the number of cyclic blocks is not a multiple of the interleaver matrix columns, resulting in increased latency and suboptimal performance.
Innovation Solution
A bit interleaving method that divides codewords into sections, where each constellation word comprises bits from multiple cyclic blocks, ensuring all bits of a section are mapped to only Q constellation words associated with that section, and applies a bit permutation process to optimize the mapping of LDPC codeword bits onto constellation bits, enhancing parallelism and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bit interleaving is applied to QC-LDPC codewords, then the interleaving process can be performed, but parallelism is impaired and latency increases when the number of cyclic blocks is not a multiple of interleaver matrix columns
Solution Approach 1:
The patent segments the QC-LDPC codeword into multiple sections, where each section contains a specific number of cyclic blocks. This segmentation allows the interleaving process to be divided into independent parallel operations on each section, improving productivity while managing latency through structured organization of the interleaving steps.
Solution Approach 2:
The patent introduces a two-dimensional interleaver matrix structure with rows and columns, where codeword bits are mapped to matrix elements. This dimensional transformation enables parallel processing across multiple rows and columns simultaneously, significantly improving interleaving efficiency and reducing latency compared to conventional one-dimensional approaches.
2Adaptability or versatility
If conventional bit interleaving is applied to QC-LDPC codewords, then the interleaving process can be performed, but the number of available interleaver configurations is limited
Solution Approach 1:
The patent employs dynamic parameters including variable row lengths, column counts, and twisting patterns that can be adjusted based on code rate and block length requirements. This dynamic configuration capability significantly increases adaptability while maintaining manageable device complexity through systematic parameter selection rather than fixed rigid structures.
Solution Approach 2:
The patent utilizes multiple configurable parameters such as the number of rows, columns, row lengths, and twisting patterns that can be changed to create different interleaver configurations. These parameter changes enable the same basic interleaver structure to adapt to various QC-LDPC code specifications, enhancing versatility without proportionally increasing device complexity.
Data Source
AI summary
A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.