Sectioned Parallel Bit Interleaving for QC LDPC Mapping

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Solution Overview

Problem

Existing bit-interleaved coding and modulation systems with quasi-cyclic low-density parity-check codes face inefficiencies in interleaving, particularly when the number of cyclic blocks in the codeword is not a multiple of the number of columns in the bit interleaver matrix, leading to impaired parallelism and increased latency, especially in iterative decoding scenarios.

Innovation Solution

A bit interleaving method that divides the codeword into sections, where each constellation word includes bits from multiple cyclic blocks, ensuring that all bits of a section are mapped to only Q constellation words associated with that section, and applies a bit permutation process to optimize the mapping of cyclic blocks to constellation words, thereby improving parallelism and reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the codeword is divided into N/M sections with each constellation word including bits from M different cyclic blocks, then parallelism is improved and latency is reduced, but the mapping complexity increases

Engineering Contradiction:
Improveinterleaving efficiencyVSAvoidmapping complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The codeword is divided into N/M sections, where each section contains M cyclic blocks. This segmentation allows independent processing of each section, enabling parallel operations and improving interleaving efficiency while managing complexity through modular structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a two-dimensional mapping structure where bits are organized both by cyclic block index and by section index. This dimensional organization transforms the complex permutation into a structured mapping that can be processed in parallel across sections while maintaining the required bit distribution properties.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Loss of time

If all bits of a given section are mapped to only Q constellation words, then latency is reduced through streamlined processing, but the interleaving thoroughness may be compromised

Engineering Contradiction:
Improveprocessing latencyVSAvoidinterleaving effectiveness
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The codeword is pre-divided into N/M sections before the bit permutation process. This preliminary organization ensures that subsequent mapping operations can proceed efficiently with reduced latency, while the pre-structured sections guarantee that all bits from each section are systematically mapped to the appropriate Q constellation words, maintaining interleaving effectiveness.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10312942B2Parallel bit interleaver
Publication Date: 2019.06.04 PANASONIC HOLDINGS CORP
  • US10312942B2 patent drawing
  • US10312942B2 patent drawing
  • US10312942B2 patent drawing

AI summary

A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each made up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.