Sector Array Addressing for ECC Management in Flash Memory
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Solution Overview
Problem
Flash memory arrays face challenges in error correction due to configuration defects like short circuits, which exceed the capacity of standard flash controllers, making it difficult to maintain data integrity and requiring additional redundancy and complex access schemes.
Innovation Solution
An addressing scheme that minimizes the impact of short circuit defects by limiting current diversion through short circuits, allowing unselected row and column lines to float, reducing the number of memory cells requiring correction, and maintaining error correction demands within the capabilities of standard flash controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If standard flash controller error correction is used, then device complexity is reduced, but reliability deteriorates when configuration defects like short circuits occur
Solution Approach 1:
The patent segments the memory array access into two distinct phases: a precharge phase where all row and column lines are simultaneously precharged to a first voltage state, and an access phase where only selected lines are actively driven. This temporal and functional segmentation isolates the effect of short circuit defects to specific phases and locations, preventing them from propagating across the entire array during normal operation.
Solution Approach 2:
The patent implements a preliminary precharge action before any data access operation. During this precharge phase, all row and column lines are simultaneously brought to a known first voltage state, ensuring that any short circuit defects are activated and stabilized before the actual data read or write operation begins. This preliminary action allows the system to prepare the memory array in a controlled manner that prevents defect propagation during subsequent access.
2Reliability
If redundancy is added to handle configuration defects, then reliability improves, but device complexity and cost increase
Solution Approach 1:
The patent changes the voltage parameter dynamics during memory access operations. By transitioning from a static voltage state to a dynamic multi-stage voltage sequence (precharge to first voltage, then selective activation), the system creates different electrical conditions that prevent short circuit defects from causing widespread errors. This parameter change approach allows standard error correction to handle defects without requiring additional redundant memory structures.
3Speed
If all row and column lines are actively driven, then access speed improves, but harmful effects of short circuits increase
Solution Approach 1:
The patent implements dynamic voltage application where the voltage state of row and column lines changes over time. During the precharge phase, all lines are simultaneously precharged. During the access phase, only the selected row and column lines are actively driven to the second voltage state while others remain at the first voltage state. This dynamic approach maintains access speed for the selected cell while preventing current diversion through short circuits in unselected lines.
Solution Approach 2:
The patent applies local quality by differentiating the voltage state and drive conditions between selected and unselected memory lines. Only the specific row and column lines involved in the current access operation are actively driven, while all other lines are left in the precharged state. This localized activation minimizes the total current flowing through the array, thereby reducing the impact of short circuit defects on unselected cells.
Data Source
AI summary
An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays.