Secure Built-In Self-Test With PRF Patterns and Scan-Out Hashing
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Solution Overview
Problem
Traditional Built-In-Self-Test (BIST) methods for Systems-on-Chip (SoC) are vulnerable to side-channel attacks and incur high area and latency overheads, making them inefficient and insecure for testing sensitive hardware intellectual property blocks.
Innovation Solution
Implement lightweight cryptography-based BIST using Pseudo-Random Functions (PRF) for secure test pattern generation and hashing, achieving low latency and high security strength with efficient area usage, utilizing algorithms like Ascon, Xoodoo, or Keccak, and precomputing round constants for multiple rounds in a single cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional BIST methods are used, then area overhead is reduced, but security strength deteriorates due to vulnerability to side-channel attacks
Solution Approach 1:
The patent changes the cryptographic parameters by selecting PRF algorithms (Ascon, Xoodoo, Keccak) with optimized round constants and state sizes that provide 128-bit security strength while minimizing hardware resource requirements. This resolves the contradiction by finding parameter settings that balance security with area efficiency
Solution Approach 2:
The patent extracts only the essential security-critical components from full cryptographic algorithms, implementing lightweight PRF versions that provide sufficient 128-bit security strength without the complete overhead of full AES or SHA-256 implementations. This selective extraction achieves security with reduced area overhead
2Reliability
If cryptography-based test pattern generation is used, then security strength is improved, but latency overhead increases
Solution Approach 1:
The patent precomputes round constants for multiple PRF rounds during design time or initialization, storing them in lookup tables or registers. This preliminary action eliminates the need for time-consuming constant generation during test execution, reducing latency while maintaining 128-bit security strength
Solution Approach 2:
The patent segments the cryptographic computation into independent rounds with precomputed constants, allowing parallel execution of multiple rounds. This segmentation reduces overall latency by enabling concurrent operations while maintaining the full security strength of the PRF algorithm
3Reliability
If AES-based secure test pattern generation is used, then security strength is improved, but area overhead increases
Solution Approach 1:
The patent replaces expensive, complex AES cryptographic hardware with lighter, disposable-like PRF implementations that provide equivalent 128-bit security strength for the specific purpose of test pattern generation. The PRF algorithms use simpler operations that require fewer hardware resources while maintaining security
Solution Approach 2:
The patent changes the cryptographic primitive from block cipher (AES) to pseudo-random function (PRF), selecting algorithms with parameters optimized for hardware efficiency. This parameter change maintains security strength while reducing the area overhead associated with AES hardware implementation
4Reliability
If SHA256-based test output hashing is used, then security strength is improved, but latency overhead increases
Solution Approach 1:
The patent extracts the essential hashing functionality from the full SHA-256 algorithm, implementing a lightweight hash function that provides sufficient 128-bit security strength for test output verification. This extraction removes unnecessary computational overhead while maintaining security
Solution Approach 2:
The patent precomputes hash values or prepares hashing constants in advance, reducing the latency of test output verification. This preliminary action allows faster comparison and validation while maintaining the security strength provided by the cryptographic hash function
Data Source
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AI summary
Techniques for secure built in self test are described. Some examples include a secure test pattern generator to generate a secure test pattern using a pseudo-random function (PRF) circuitry; a scan out hash engine to hash a scan out of a circuit to be tested; and a comparison circuit to compare the hashed scan out to a known value to verify the hash.