Secure Boot Firmware Verification with Parallel Core Execution
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Solution Overview
Problem
Existing processing devices face challenges in efficiently utilizing their security cores during the Chain of Trust process, leading to suboptimal booting speed and device performance.
Innovation Solution
A processing device with a security core that operates a Root of Trust and performs integrity checks on firmware, utilizing a crypto accelerator for encryption operations, and includes an immutable memory to store unalterable data, allowing parallel operation of firmware integrity checks and execution, with the security core managing the main core's operations to ensure secure booting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the security core performs integrity checks sequentially for each firmware, then the security and reliability are ensured, but the booting speed and device performance deteriorate
Solution Approach 1:
The security core performs integrity checks on firmware in advance during the booting process, validating firmware before execution. The Root of Trust verifies firmware integrity prior to loading, ensuring security while enabling faster subsequent operations since validation is completed beforehand
Solution Approach 2:
The processing device is divided into separate security core and main core domains, with the security core dedicated to integrity verification tasks and the main core handling execution. This segmentation allows parallel operation of security checks and firmware execution, improving overall booting speed while maintaining reliability
2Reliability
If the security core performs all integrity check operations, then the security is maximized, but the productivity and resource utilization of the security core worsen due to overload
Solution Approach 1:
Encryption operations are extracted from the security core and delegated to a dedicated crypto accelerator. This extraction allows the security core to focus on high-level security management and integrity verification, while the crypto accelerator handles computationally intensive encryption tasks, improving overall system productivity
Solution Approach 2:
A crypto accelerator is introduced as an intermediary component between the security core and firmware execution. This intermediary handles encryption/decryption operations, freeing the security core from resource-intensive cryptographic computations and improving its utilization efficiency for security-critical tasks
Data Source
AI summary
Provided are a processing device and a method for secure booting thereof, in which the processing device includes a security core that operates a Root of Trust and sequentially performs an integrity check on first firmware and second firmware through the Root of Trust, a main core that sequentially operates the first firmware and the second firmware, a non-volatile memory storing the first firmware and the second firmware, and a first volatile memory that loads the first firmware and the second firmware from a main core domain of the main core and operates the loaded firmware with the main core.