Secure Boot Processor Segmentation for Watchdog Timeout Prevention
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Solution Overview
Problem
The integration of watchdog timer (WDT) and secure boot technology in systems can lead to unintended system resets due to timeout issues during program verification, preventing normal system initiation, especially when verification takes longer than expected.
Innovation Solution
An information processing apparatus is designed with a first processor for program validity verification, a control circuit for issuing a system reset signal in case of no external access, and a second processor to execute validated programs, where the second processor accesses the control circuit after verification, and periodically clears the WDT counter to prevent timeouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If secure boot verification is performed before main processor starts, then system security is improved, but system initiation time increases and may cause WDT timeout
Solution Approach 1:
The system is divided into two processors: a first processor (supplemental processor) dedicated to secure boot verification and a second processor (main processor) for executing the verified program. This segmentation allows verification to occur in parallel with WDT monitoring, preventing timeout while maintaining security.
Solution Approach 2:
The control circuit acts as an intermediary between the processors and the WDT. It receives access requests from both processors and selectively allows or blocks them based on the verification state, preventing the main processor from accessing the WDT before verification completes.
2Duration of action of moving object
If WDT timeout threshold is extended to accommodate verification time, then system initiation is allowed to complete, but system responsiveness to actual hangs decreases
Solution Approach 1:
By separating verification functions to a dedicated first processor, the system can maintain a normal WDT timeout threshold while allowing extended verification time, as the verification process no longer competes for WDT access with the main execution processor.
3Reliability
If main processor is blocked during verification, then WDT timeout is prevented, but system operation is delayed
Solution Approach 1:
The system uses two separate processors: the first processor handles verification and WDT access, while the second processor is prepared to execute the program immediately after verification. This parallel structure prevents blocking while ensuring WDT timeout prevention.
Solution Approach 2:
The first processor performs verification in advance before the main processor needs to execute the program. The control circuit is configured to allow main processor access only after verification completes, ensuring readiness without delay.
Data Source
AI summary
There is provided an information processing apparatus that includes a first processor configured to verify a validity of a program, a control circuit configured to issue a system reset signal in a case where there is no access from outside for a predetermined period, and a second processor configured to execute the program that has been determined as valid by the first processor, and to become accessible to the control circuit after the program is initiated. The first processor is configured to access the control circuit before the second processor becomes accessible to the control circuit.