Secure Boot via Write-Once Register and ROM Flash Segmentation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Electronic systems lack secure authentication mechanisms during the boot process, making them vulnerable to tampering and integrity compromise, particularly in the BIOS code stored in flash memory.

Innovation Solution

An electronic device architecture that includes a write-once-then-read-only register, a chipset with a read-only memory and flash memory, where a CPU reset signal determines which instruction to retrieve from either memory block, allowing for secure verification of the BIOS code before executing it, using a security verification code stored in the read-only memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the BIOS code is stored in flash memory for flexibility and upgradability, then the adaptability is improved, but the security and integrity protection deteriorates

Engineering Contradiction:
ImproveBIOS code upgradabilityVSAvoidBIOS code integrity
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent segments the memory system into two distinct parts: flash memory for storing upgradable BIOS code and a read-only memory (such as EEPROM or ROM) for storing immutable security verification codes. This segmentation allows the system to maintain both adaptability (through flash memory updates) and reliability (through read-only security verification), resolving the contradiction between flexibility and security.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If no authentication mechanism is implemented during boot process to maintain simplicity, then the device complexity is reduced, but the security vulnerability increases

Engineering Contradiction:
Improveboot process complexityVSAvoidBIOS tampering risk
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent implements preliminary action by executing security verification codes from read-only memory before executing the BIOS code from flash memory during the boot process. This preliminary security check is integrated into the existing boot sequence, adding protection without fundamentally redesigning the boot process. The CPU automatically executes the verification code first, then proceeds to execute the BIOS code if verification succeeds, thus maintaining relative simplicity while enhancing security.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If a security verification code is executed before BIOS code to ensure integrity, then the reliability is improved, but the boot process time increases

Engineering Contradiction:
ImproveBIOS code verificationVSAvoidboot process time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by executing only the essential security verification code from read-only memory before BIOS execution, rather than implementing comprehensive security checks. The verification code is designed to perform only the critical function of checking BIOS integrity, avoiding unnecessary verification steps. This partial verification approach provides sufficient security protection while minimizing the time overhead during the boot process.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9098301B2Electronic device and booting method
Publication Date: 2015.08.04 VIA TECH INC
  • US9098301B2 patent drawing
  • US9098301B2 patent drawing
  • US9098301B2 patent drawing

AI summary

The present invention provides an electronic device including a write-once-then-read-only register, a chipset, a read-only memory, a flash memory and a central processor. The write-once-then-read-only register is arranged to store a determination value. The chipset is arranged to produce a CPU reset signal. The read-only memory is implemented in the chipset, and has a first memory block which corresponds to a predetermined address and is used to store a first instruction. The flash memory is coupled to the chipset, and has a second memory block which corresponds to the predetermined address and is used to store a second instruction. The central processor is arranged to determine the location of the predetermined address according to the CPU reset signal and the determination value.