Secure Boot ROM Patching via OTP Storage
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Solution Overview
Problem
The existing on-chip ROM patch mechanisms in System-on-Chip (SoC) devices are insecure and costly to revise, leading to potential compromise of the secure boot process and significant delays in product launches due to the need for new silicon wafer masks.
Innovation Solution
Implementing a secure on-chip ROM patch mechanism using one-time programmable (OTP) storage circuitry, such as electronic fuses, to securely store and lock ROM patch code, allowing for secure patching without affecting the integrity of the secure boot process, eliminating the need for new silicon wafer masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing on-chip ROM patch mechanisms are enabled, then ROM can be patched to correct problems or add capability, but security is compromised due to potential unauthorized changes
Solution Approach 1:
The patent introduces a secure boot ROM patch mechanism that acts as an intermediary between the boot ROM and patch code. The mechanism includes a patch loader that verifies patch authenticity using cryptographic signatures and a patch application mechanism that applies only verified patches. This intermediary layer enables ROM patching capability while maintaining secure boot integrity by filtering out unauthorized changes.
Solution Approach 2:
The patent changes the security parameters of the ROM patching system by implementing cryptographic verification mechanisms. Patch code is signed with a private key and verified using a public key stored in the secure boot ROM. This parameter change from unverified to verified patching enables adaptability while maintaining reliability through cryptographic security measures.
2Reliability
If ROM patching is disabled for security, then secure boot integrity is maintained, but product launch delays occur due to expensive mask revisions
Solution Approach 1:
The secure boot ROM patch mechanism serves as an intermediary that eliminates the need for mask revisions. Instead of physically revising silicon masks, the system uses a software-based patch loading mechanism that reads patch code from external storage and applies it to the ROM during boot. This intermediary approach maintains secure boot integrity while avoiding the time-consuming mask revision process.
Solution Approach 2:
The patent implements a copying mechanism where patch code is copied from external storage media to the ROM during the boot process. The patch loader reads patch instructions from external storage and copies them to the appropriate ROM locations. This copying approach replaces the traditional mask revision process, eliminating product launch delays while maintaining security through verified patch application.
3Manufacturing precision
If silicon wafer masks are revised for ROM fixes, then ROM correctness is improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent replaces the physical mask copying process with a digital copying mechanism. Instead of creating new silicon wafer masks, the system copies patch code digitally from external storage to ROM during boot. This digital copying approach maintains ROM correctness through verified patch application while dramatically reducing manufacturing costs by eliminating the need for expensive C40 ROM mask revisions.
Solution Approach 2:
The patent uses disposable external storage media to store patch code instead of expensive reusable silicon masks. The patch code is loaded from inexpensive external storage during the boot process and applied to the ROM. This approach replaces costly mask revisions with cheap, disposable storage media, reducing manufacturing costs while maintaining ROM correctness through verified patch application.
Data Source
AI summary
A data processing system includes a boot read only memory (ROM) configured to store boot code; one time programmable (OTP) storage circuitry configured to store patch instructions; a random access memory (RAM); and a processor coupled to the boot ROM, the OTP storage circuitry, and the RAM. The processor is configured to: in response to a reset of the data processing system, copy one or more patch instructions from the OTP storage circuitry into the RAM, and during execution of the boot code, execute a patch instruction from the RAM in place of a boot instruction of the boot code.