Secure Cache Slice Access Using Master-SCID Mapping

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Solution Overview

Problem

Modern computing systems face issues with unauthorized cache access due to incorrect or malicious use of Sub-Cache Index IDs (SCIDs), leading to performance degradation, operation failures, and security risks.

Innovation Solution

Implementing a mapping table to verify cache access packets using master and sub-cache index identifiers, rejecting unauthorized access, and generating error or security warnings to ensure proper cache access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If cache access is allowed without verification, then access speed is improved, but security and reliability deteriorate due to unauthorized access

Engineering Contradiction:
Improvecache access speedVSAvoidcache access security
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The mapping table is pre-populated with authorized master-subcache index identifier associations before cache access operations begin. This preliminary configuration enables the interconnect controller to quickly verify authorization by simply checking whether the requesting master's identifier and target subcache index identifier match an entry in the pre-configured mapping table, rather than performing complex authorization checks during each access operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The mapping table acts as an intermediary data structure between the master and the cache slices. It mediates the access relationship by storing the authorized associations, allowing the interconnect controller to enforce security policies without directly implementing complex authorization logic. This intermediary layer simplifies the access control mechanism while maintaining security.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a mapping table verification mechanism is implemented, then security and reliability are improved, but device complexity increases

Engineering Contradiction:
Improvecache access securityVSAvoidaccess control mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The cache memory is divided into multiple independent slices, each accessible only to specific masters as defined in the mapping table. This segmentation isolates cache resources and enables fine-grained access control. The mapping table itself is segmented into discrete entries, each representing an authorized master-subcache index identifier association, making the verification process modular and manageable.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The mapping table is designed to be self-contained with all necessary authorization information. The interconnect controller performs self-verification by checking whether the requesting master's identifier and target subcache index identifier exist as an associated pair in the mapping table, without requiring external authorization services or complex policy evaluation logic.

Inventive Principle:
Principle #25Self-service

3Ease of operation

If unauthorized access is permitted, then ease of operation is improved, but system integrity deteriorates due to performance degradation and errors

Engineering Contradiction:
Improvecache access convenienceVSAvoidsystem integrity
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The mapping table verification mechanism provides immediate feedback to the interconnect controller about whether a cache access request is authorized. When a master attempts to access a subcache index identifier that is not associated with it in the mapping table, the verification mechanism instantly identifies this as unauthorized access and blocks the request, preventing performance degradation and errors before they occur.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12517840B2Cache access rejection for unauthorized secure cache ID from known master
Publication Date: 2026.01.06 QUALCOMM INC
  • US12517840B2 patent drawing
  • US12517840B2 patent drawing
  • US12517840B2 patent drawing

AI summary

An interconnect controller is coupled to a cache and coupled to a plurality of masters and configured to receive a cache access packet from a master. The cache access packet includes a first master identifier to identify the master, a first sub-cache index identifier to identify a slice of the cache, and an operation to be performed on the cache. A mapping table has master identifiers associated with sub-cache index identifiers and compare logic compares the first master identifier and the first sub-cache index identifier to the mapping table. The interconnect controller rejects the cache access packet in response to the first master identifier not being associated with the first sub-cache index identifier in the mapping table.