Secure Carry-Lookahead Adder Masking Logic

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Solution Overview

Problem

Existing secure adders in encryption and decryption applications fail to perform secure addition operations without revealing the original values of input data, leading to inadequate protection mechanisms and higher manufacturing costs due to the need for complex logic units.

Innovation Solution

A secure carry-lookahead adder is designed, incorporating a mask generator and carry-lookahead adder with XOR gates, mask units, and a carry-lookahead generator, which performs masked operations using random mask values to protect input data during addition, ensuring the output remains masked.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If complex logic units are used to perform secure addition operations, then security protection is improved, but manufacturing cost increases

Engineering Contradiction:
Improvesecurity protectionVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent changes the operational parameters by introducing mask values that transform the addition operation into masked addition operations. This allows standard adders to perform secure computations by operating on masked data rather than plain data, achieving security without requiring specialized complex logic units.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

Mask values serve as intermediaries between the plain input data and the adder operation. The mask units apply these intermediary mask values to the input data before addition, and the results remain masked throughout the computation, protecting the original data values while using standard adder logic.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If complex logic units are used to perform secure addition operations, then security protection is improved, but device complexity increases

Engineering Contradiction:
Improvesecurity protectionVSAvoidlogic units
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The secure adder is segmented into functional modules: mask units for applying mask values, standard adders for performing masked addition, and logic circuits for generating mask values. This segmentation allows each component to remain relatively simple while the system as a whole achieves security through their coordinated operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Mask values act as intermediaries that enable security protection without requiring complex logic units. The mask units and standard adders work together with these intermediary values to achieve secure computation using relatively simple, modular components rather than complex specialized logic.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If standard adders are used without mask protection, then device complexity is reduced, but security protection is weakened

Engineering Contradiction:
Improvelogic unitsVSAvoidsecurity protection
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent changes the data representation parameter by introducing mask values that transform plain data into masked data. Standard adders operate on these masked values, and the mask units manage the masking process, achieving security protection while keeping the adder logic simple and standard.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20230214183A1Carry-lookahead adder, secure adder and method for performing carry-lookahead addition
Publication Date: 2023.07.06 NUVOTON
  • US20230214183A1 patent drawing
  • US20230214183A1 patent drawing
  • US20230214183A1 patent drawing

AI summary

A carry-lookahead adder is provided. First XOR gate receives a first mask value and a second mask value to provide a variable. First mask unit performs a first mask operation on first input data with the variable to obtain first masked data. A half adder receives the first masked data and second input data to generate a propagation value and an intermediate generation value. Second mask unit performs a second mask operation on the propagation value with a third mask value to obtain second masked data. A logic circuit provides a generation value according to the propagation value, the intermediate generation value and the second mask value. A carry-lookahead generator provides a carry output and a carry value according to a carry input, the generation value and the propagation value. Second XOR gate receives the second masked data and the carry value to provide a sum output.