Secure Carry-Lookahead Adder Masking Circuit
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Solution Overview
Problem
Existing adders in encryption and decryption applications lack secure mechanisms to perform addition operations without revealing the original input data, necessitating a secure adder that can maintain mask protection during calculations.
Innovation Solution
A secure carry-lookahead adder is designed with multiple mask units, XOR gates, a half adder, logic circuit, and a carry-lookahead generator, which performs mask operations on input data using different mask values to generate masked data and maintain protection, ensuring the output is masked and secure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a secure adder is designed to perform secure addition operations with mask protection, then security is improved, but device complexity increases
Solution Approach 1:
The secure adder is divided into multiple functional modules: mask generation unit, mask operation units (first, second, third mask units), half adder, logic circuit, and carry-lookahead generator. Each module performs a specific function in the secure addition process, allowing the complex secure addition operation to be broken down into manageable segments that can be implemented and analyzed separately.
Solution Approach 2:
Mask values serve as intermediaries between the input data and the addition operation. The first mask unit performs mask operation on first input data with a first mask value to obtain first masked data, the second mask unit performs mask operation on second input data with a second mask value to obtain second masked data, and the third mask unit performs mask operation on the propagation value with a third mask value. These mask intermediaries protect the original data throughout the computation process.
2Reliability
If multiple mask units and logic circuits are added to ensure secure addition, then security is improved, but manufacturing cost increases
Solution Approach 1:
The mask units perform multiple functions within the secure adder architecture. The same mask operation mechanism is reused across different stages: masking input data, masking intermediate propagation values, and masking final results. This universal masking approach reduces the need for entirely separate security mechanisms for each operation stage, thereby controlling manufacturing costs while maintaining security.
Solution Approach 2:
The invention uses different mask values (first mask value, second mask value, third mask value) at different stages of the addition process. These parameter changes in the form of varying mask values allow the same hardware structure to provide security throughout the computation without requiring additional security-specific hardware for each stage, thus managing manufacturing costs.
3Reliability
If additional logic units are incorporated to maintain mask protection during calculation, then security is improved, but power consumption increases
Solution Approach 1:
The mask operation is applied continuously throughout the addition process rather than being applied only at specific stages. The first mask unit masks input data before addition, the third mask unit masks the propagation value during the carry-lookahead process, and the final result is also masked. This continuous masking ensures security is maintained throughout the entire computation, preventing the need for additional verification or re-masking operations that would increase power consumption.
4Productivity
If a carry-lookahead structure is used to improve addition speed, then productivity is improved, but device complexity increases
Solution Approach 1:
The carry-lookahead generator is segmented into multiple logic circuits that independently calculate carry signals for different bit positions. Instead of a single sequential carry calculation, the generator divides the addition into segments that can compute carries in parallel, significantly improving addition speed while keeping each individual logic circuit relatively simple.
Solution Approach 2:
The carry-lookahead generator performs preliminary calculation of carry signals before the actual addition is completed. By pre-computing the carry values that will be needed for each bit position based on the input operands, the addition operation can proceed more quickly without waiting for sequential carry propagation, thus improving productivity.
Data Source
AI summary
A carry-lookahead adder is provided. A first mask unit performs first mask operation on first input data with the first mask value to obtain first masked data. A second mask unit performs second mask operation on second input data with the second mask value to obtain second masked data. A first XOR gate receives the first and second mask values to provide a variable value. A half adder receives the first and second masked data to generate a propagation value and an intermediate generation value. A third mask unit performs third mask operation on the propagation value with the third mask value to obtain the third masked data. A carry-lookahead generator provides the carry output and the carry value according to carry input, the generation value, and the propagation value. The second XOR gate receives the third masked data and the carry value to provide the sum output.