Secure Chip Biased Wells Fault Injection Detection
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Solution Overview
Problem
Electronic chips containing confidential information are vulnerable to fault injection attacks, such as those using laser beams or electromagnetic disturbances, which disrupt the chip's operation and allow hackers to extract sensitive data.
Innovation Solution
The implementation of a secure electronic chip design featuring biased semiconductor wells and a detection circuit that monitors bias currents, producing an alert signal when the current exceeds a threshold, triggering countermeasures like stopping the chip's activity or destroying confidential data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional chip structures are used, then manufacturing is simple, but the chip is vulnerable to fault injection attacks
Solution Approach 1:
The chip is divided into multiple independently biased semiconductor wells (first wells and second wells with opposite conductivity types). Each well can be monitored separately by dedicated detection circuits, allowing localized security monitoring without requiring complete restructuring of the entire chip. This segmentation enables selective protection while maintaining overall chip functionality.
Solution Approach 2:
The detection circuits continuously monitor bias currents before attacks can extract confidential information. By establishing baseline current levels and setting threshold alerts in advance, the system detects anomalies (such as laser-induced current changes) before they can compromise security, enabling preventive countermeasures to be taken.
2Reliability
If detection circuits are added to monitor bias current, then attack detection capability is improved, but device complexity increases
Solution Approach 1:
The detection circuits utilize the existing bias current that flows through the semiconductor wells during normal operation. Rather than requiring separate test currents or additional external monitoring equipment, the system repurposes the operational bias current itself as the detection signal, allowing the chip to monitor its own security status using resources already present in its normal functioning.
Solution Approach 2:
The bias current serving the dual function of both powering the semiconductor wells during normal operation and providing the detection signal for attack monitoring. This multi-functionality eliminates the need for separate test circuits or additional current sources, reducing overall device complexity while maintaining comprehensive security monitoring capability.
3Measurement precision
If multiple biased wells are implemented with separate detection circuits, then detection precision is improved, but manufacturing complexity increases
Solution Approach 1:
Different semiconductor wells are doped with opposite conductivity types (n-type and p-type) to create locally distinct electrical characteristics. Each well type has tailored detection circuits optimized for its specific current characteristics, allowing precise detection of attack-induced anomalies in each region while maintaining compatibility with standard semiconductor manufacturing processes for doped structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively protects electronic chips from fault injection attacks by detecting even low-level disturbances, enabling immediate countermeasures to prevent data extraction and ensuring the chip's security against various attack methods.
Implementation Method 1
a circuit for detecting the bias current of the wells
Implementation Method 2
the detection circuit comprises a resistive element through which the bias current flows, the detection circuit being suitable for detecting a voltage across the terminals of the resistive element
Data Source
Figure 1~2
Figure 3~4
Figure 5A~5B
AI summary
The invention relates to a secure electronic chip (50) comprising a plurality of polarized semiconductor boxes (3, 33) and a detection circuit (57, 61) for the polarization current of the boxes.