Secure Chip Debug Data Collection via Power-On-Reset Engine
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Solution Overview
Problem
Modern processor chips in secure mode disable debug interfaces, making it impossible to collect debug data externally, and existing solutions face challenges in implementing secure access and are prone to breaking chip security or functionality.
Innovation Solution
A processor chip mechanism that uses a power-on-reset engine to monitor health and collect debug data in secure mode by storing it in a read-only buffer or directly outputting it, allowing access even when debug interfaces are disabled, using health monitoring logic to detect errors and initiate debug data collection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If debug interfaces are disabled in secure mode to prevent unauthorized access, then chip security is improved, but ability to collect debug data is lost
Solution Approach 1:
The patent segments the debug interface into two distinct modes: a secure mode where the interface is disabled to prevent unauthorized access, and a debug mode where the interface is enabled to allow external access for collecting debug data. This segmentation allows the system to maintain security during normal operation while enabling debugging when needed, resolving the contradiction between security and debug data accessibility.
Solution Approach 2:
The patent implements a dynamic debug interface that can change its state between enabled and disabled based on operational mode. The interface transitions from a static disabled state in secure mode to an enabled state in debug mode, allowing the system to adapt its security posture according to the current operational requirements, thus balancing security and debug accessibility.
2Loss of information
If JTAG interface is used for debug access, then ability to extract debug information is improved, but security verification becomes difficult and chip complexity increases
Solution Approach 1:
The patent extracts the debug data collection functionality from the traditional JTAG interface approach and implements it through a simplified mechanism that leverages existing chip resources. Instead of requiring complex JTAG security verification, the system uses a straightforward mode transition and interface enablement mechanism that reduces security verification complexity while maintaining debug information extraction capability.
3Ease of operation
If register exceptions are added in silicon to allow specific register access, then specific debug access is improved, but adaptability to add new exceptions later is lost
Solution Approach 1:
The patent changes the operational parameters of the debug interface by introducing a software-configurable exception mechanism that replaces hard-coded silicon exceptions. This allows the system to dynamically enable or disable access to specific registers through software control, providing both ease of operation for current needs and adaptability for future requirements without modifying the physical chip structure.
Data Source
AI summary
Mechanisms, in a processor chip, are provided for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation. The processor chip is placed into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on a debug interface of the processor chip. A triggering condition of the processor chip is detected that is a trigger for initiated debug data collection from the on-chip logic. Debug data collection is performed from the on-chip logic to generate debug data. Data is output, by the processor chip to an external mechanism, on the debug interface based on the debug data.