Secure Chip Layout Using Dual-Resolution Lithography
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Bulk manufacturing of semiconductor chips using optical lithography introduces variability and makes it impractical to embed unique identification data, as masks are costly and vulnerable to reverse engineering, while e-beam lithography is unsuitable for bulk production due to cost and speed limitations.
Innovation Solution
Implementing a dual lithographic process with a first lithographic process for bulk manufacturing and a second, finer resolution process for specific circuits, making it difficult for attackers to reverse engineer the chip by introducing manufacturing variations that are not resolvable at the initial imaging resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If optical lithography is used for bulk manufacturing, then productivity is improved, but manufacturing precision deteriorates due to variability and inability to embed unique identification data
Solution Approach 1:
The patent divides the chip into two distinct circuit portions: a first circuit portion manufactured using optical lithography for bulk production, and a second circuit portion manufactured using e-beam lithography for precise unique identification embedding. This segmentation allows each portion to be optimized for its specific manufacturing requirements, resolving the contradiction between bulk manufacturing productivity and precision unique identification capability.
2Manufacturing precision
If masks are used for embedding unique identification data, then manufacturing precision is improved, but device complexity increases due to costly mask fabrication and reverse engineering vulnerabilities
Solution Approach 1:
The patent extracts the unique identification data embedding function from the main bulk manufacturing process. By using e-beam lithography specifically for the second circuit portion that contains unique identification data, the complex mask fabrication process is eliminated for this critical function, while the bulk manufacturing process remains simple and efficient.
3Manufacturing precision
If e-beam lithography is used for unique identification embedding, then manufacturing precision is improved, but productivity deteriorates due to cost and speed limitations
Solution Approach 1:
The patent applies different manufacturing qualities to different parts of the chip: optical lithography is used for the first circuit portion that does not require high precision, while e-beam lithography is used for the second circuit portion that requires fine resolution for unique identification embedding. This local differentiation of manufacturing quality allows high precision where needed while maintaining overall productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the resistance of silicon chips to reverse engineering by ensuring that critical logic blocks are formed using a finer resolution process, making it challenging for attackers to clone the chip and maintain its unique identification and security features.
Implementation Method 1
a first circuit layout is applied to the silicon chip to form a first circuit at a first characteristic resolution
Implementation Method 2
a second circuit layout is applied to the silicon chip to form a second circuit at a second characteristic resolution which is finer than the first characteristic resolution
Data Source
Figure 1
Figure 2A~2B
Figure 3~5
AI summary
There is provided a method of securely embedding a circuit on a semiconductor wafer to form a reverse engineering resistant semiconductor chip. The method comprises applying, a first circuit layout to the semiconductor wafer using first lithographic process, wherein the first lithographic process has a first characteristic resolution and applying, a second circuit layout to the semiconductor wafer using a second lithographic process to form the securely embedded circuit. The second lithographic process has a second characteristic resolution, wherein the second circuit layout defines a set of functional elements in the second circuit that cannot be resolved at the first characteristic resolution.