Delayed Redundant Secure Circuits Against Synchronized Fault Attacks
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Solution Overview
Problem
Existing cryptographic hardware is vulnerable to fault attacks where attackers can induce faults and analyze the results to obtain secret information, such as cryptographic keys, by synchronizing attacks across multiple instances of secure circuits with precise timing.
Innovation Solution
Implementing redundant secure circuits with delay mechanisms, where inputs and outputs are synchronized through delay circuits with varying delays (N and M) to ensure that outputs from different instances are compared at the same time, making synchronized attacks more difficult by introducing additional errors if the attacker fails to synchronize correctly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant secure circuits are implemented without delay mechanisms, then the circuit complexity increases, but the vulnerability to synchronized fault attacks remains high
Solution Approach 1:
The patent applies preliminary action by introducing delay circuits before the secure circuits to desynchronize their operation in advance. The first delay circuit delays the input to the first secure circuit, and the second delay circuit delays the input to the second secure circuit, ensuring that even if an attacker injects synchronized faults, the faults will be applied at different effective times within the secure circuits, thereby preventing successful synchronized fault attacks.
2Device complexity
If delay circuits with fixed delays are used, then the circuit structure is simple, but attackers can more easily synchronize their attacks
Solution Approach 1:
The patent applies dynamics by making the delay values variable rather than fixed. The first delay circuit has a first delay value and the second delay circuit has a second delay value, where these delay values can be changed dynamically. This dynamic adjustment prevents attackers from easily determining and synchronizing their fault injection timing, as the relative timing between the two secure circuits changes over time.
3Ease of operation
If the delay values are constant, then the timing prediction is easy for attackers, but the circuit operation is straightforward
Solution Approach 1:
The patent applies parameter changes by varying the delay values of the delay circuits. The first delay circuit and second delay circuit have delay values that can be changed, ensuring that the timing relationship between the two secure circuits is not constant. This makes it difficult for attackers to predict when faults should be injected to achieve synchronization, thereby enhancing protection against synchronized fault attacks while maintaining straightforward circuit operation.
Data Source
AI summary
Various embodiments relate to a circuit, including: a first secure circuit configured to receive an input and to produce a first output; a first delay circuit configured to receive the first output and to produce a first delayed output delayed by a time N; a second delay circuit configured to receive the input and to produce a delayed input delayed by a time N; a second secure circuit configured to receive the delayed input and to produce a second delayed output; and a comparator configured to compare the first delayed output to the second delayed output and to produce a result, wherein the result is one of the first delayed output or second delayed output when the first delayed output matches the second delayed output and the result is an error value when the first delayed output does not match the second delayed output.