Secure Coprocessor for Unresponsive SoC Debugging
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Solution Overview
Problem
Traditional hardware debugging systems face limitations due to dependence on live CPU cores, high performance penalties from round-trip data traffic, and costly extensions in SoC Design For Test and Design For Debug designs, especially when CPU cores are unresponsive or hung.
Innovation Solution
Implementing a secure coprocessor that works in parallel with CPU cores to perform computationally intensive tasks, including page table walks, and manages debug operations, reducing the need for multiple round-trip communications and enabling data retrieval from unresponsive processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional JTAG debugging is used with round-trip communication between host and target, then debug functionality can be provided, but performance penalty increases due to extensive data traffic
Solution Approach 1:
The patent extracts critical debugging functions from the host PC and relocates them to a coprocessor embedded within the target device. This includes virtual address to physical address translation, memory management, and debug data processing. By taking out these functions from the host and placing them locally in the coprocessor, the system eliminates extensive round-trip data traffic between host and target, thereby resolving the performance penalty while maintaining full debug functionality.
Solution Approach 2:
The coprocessor acts as an intermediary between the host debugging tool and the target CPU cores. It receives debug requests from the host, performs local processing including address translation and memory access, and returns results to the host. This intermediary approach reduces the need for direct host-target communication for every debug operation, significantly improving performance by minimizing round-trip traffic.
2Adaptability or versatility
If CPU cores are used for debugging operations, then debug features can be accessed, but debugging fails when CPU cores are unresponsive or hung
Solution Approach 1:
The patent segments the debugging system into independent components: the host debugging tool, the coprocessor, and the target CPU cores. The coprocessor is given independent debugging capabilities that do not depend on CPU responsiveness. It can directly access memory, perform address translation, and retrieve debug information independently of the CPU state, allowing debugging to continue even when CPU cores are hung or unresponsive.
Solution Approach 2:
The coprocessor provides self-service debugging capabilities by independently handling address translation, memory access, and debug data retrieval without requiring CPU intervention. It maintains its own execution pipeline and can service debug requests autonomously, ensuring that debugging functionality remains available even when the target CPU cores are unresponsive or hung.
3Adaptability or versatility
If new debug features are added to SoC designs, then debugging capability is enhanced, but cost increases due to Design For Test and Design For Debug extensions
Solution Approach 1:
The coprocessor is designed as a universal debugging platform that can handle multiple debug functions through software configuration rather than hardware extensions. It provides virtual address to physical address translation, memory management, breakpoint handling, and various debug data retrieval capabilities through a unified architecture. This multi-functionality allows new debug features to be added via software updates without requiring costly hardware modifications to the SoC design.
Solution Approach 2:
The system uses parameter changes and configuration to enable different debug features rather than hardwired hardware extensions. The coprocessor can be reconfigured through software to provide different debugging capabilities, allowing the same hardware platform to adapt to new debug requirements without physical modifications. This approach significantly reduces the cost associated with Design For Test and Design For Debug extensions.
Data Source
AI summary
Systems, apparatuses, and methods for implementing debug features on a secure coprocessor to handle communication and computation between a debug tool and a debug target are disclosed. A debug tool generates a graphical user interface (GUI) to display debug information to a user for help in debugging a debug target such as a system on chip (SoC). A secure coprocessor is embedded on the debug target, and the secure coprocessor receives debug requests generated by the debug tool. The secure coprocessor performs various computation tasks and/or other operations to prevent multiple round-trip messages being sent back and forth between the debug tool and the debug target. The secure coprocessor is able to access system memory and determine a status of a processor being tested even when the processor becomes unresponsive.