Secure Data Comparison Circuit with Pre-computed Verification
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Solution Overview
Problem
Secure integrated circuits, such as smart card ICs, are vulnerable to fraud attacks like fault or error injection, which disrupt sensitive operations by introducing disturbances in supply voltage, data, or clock signals, allowing attackers to deduce secret keys or cryptography algorithm structures.
Innovation Solution
A method and circuit for securing program execution by computing comparison variables before and after data comparisons, checking their consistency with the selected program operations, and enabling error signals for inconsistencies, using binary comparison variables derived from bitwise operations and flags to verify the integrity of data comparison results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data comparison operations are performed in secure integrated circuits, then authentication and cryptographic operations can be executed, but the circuit becomes vulnerable to fault injection attacks that disrupt the comparison process
Solution Approach 1:
The patent computes comparison variables (XOR result, AND of complements, OR of results) before the actual data comparison operation. These pre-computed variables serve as expected values that can be used to verify the correctness of the comparison result afterward, preventing fault injection attacks from undetectedly altering the comparison outcome
Solution Approach 2:
The patent implements a verification mechanism that checks whether the pre-computed comparison variables are consistent with the actual comparison result. If inconsistency is detected (indicating a fault injection attack), an error signal is generated, providing feedback that the comparison was compromised and the result should be rejected
2Reliability
If multiple comparison variables are computed and checked for consistency, then detection of tampering during data comparison is improved, but the computational overhead and complexity of the operation increases
Solution Approach 1:
The patent breaks down the comparison verification into multiple independent comparison variables, each capturing different aspects of the data relationship (XOR for difference detection, AND of complements for equality confirmation, OR for comprehensive coverage). This segmentation allows parallel computation and independent verification of each variable's consistency with the comparison result
Solution Approach 2:
The patent transforms the single comparison result into multiple derived parameters (comparison variables) that can be independently computed and verified. By changing the representation from a single binary result to multiple bitwise operations, the system achieves more robust verification while using standard processor instructions
Data Source
AI summary
This disclosure relates to a method for securing the execution of a program by a processor, including a comparison instruction for comparing two data items, followed by a program operation which is selected as a function of a comparison result provided by the comparison instruction. The method may include, before the execution of the comparison instruction, calculating in various ways comparison data representative of the equality of the data to be compared, after the execution of the comparison instruction, verifying whether the comparison data calculated are consistent with the fact that the program operation is selected or not selected, and activating an error signal if the comparison data are mutually inconsistent or inconsistent with the result of the comparison.