Secure Demand Paging System for Memory Security and Cost Reduction
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Solution Overview
Problem
Current technologies face challenges in securely handling large amounts of software program code and data in electronic computing and communications systems without requiring substantial additional on-chip memory, especially in wireless communications where security and cost-effectiveness are crucial.
Innovation Solution
A secure demand paging system that includes a processor with internal and external memory, a security circuit, and a microprocessor capable of multi-threading and secure data processing, allowing for secure page configuration, confidentiality, and integrity processing, and efficient page replacement strategies to manage memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If substantial amounts of on-chip memory are added to handle large software and data, then security and processing capability are improved, but manufacturing cost and device complexity increase
Solution Approach 1:
The memory system is segmented into secure on-chip memory for critical security data and insecure off-chip memory for bulk data storage. The secure memory controller manages this segmentation, allowing the system to maintain security for essential operations while using larger, cheaper off-chip memory for non-critical data, thus improving security without proportionally increasing device complexity
Solution Approach 2:
A secure memory controller acts as an intermediary between the processor and the segmented memory system. It transparently manages data encryption, decryption, and integrity verification between secure and insecure memory regions, enabling security improvements without requiring the processor itself to become more complex
2Productivity
If substantial amounts of on-chip memory are added to handle large software and data, then processing capability is improved, but manufacturing cost increases
Solution Approach 1:
Memory capacity is segmented between small expensive on-chip secure memory and large cheap off-chip insecure memory. The secure memory controller enables the system to access the combined capacity of both memory types, providing large processing capability while maintaining cost-effectiveness by using inexpensive off-chip memory for bulk storage
Solution Approach 2:
Data is copied between secure on-chip memory and insecure off-chip memory as needed. Frequently accessed security-critical data resides in on-chip memory for fast processing, while less frequently accessed data is stored in off-chip memory, providing large processing capability without the cost of keeping all data in expensive on-chip memory
3Reliability
If secure demand paging with encryption and integrity check is implemented, then security is improved, but processing time and energy consumption increase
Solution Approach 1:
Data is encrypted and integrity-checked in advance when written to off-chip memory, and decryption/verification is performed during the paging-in process rather than during active processing. This preliminary action approach ensures security without adding significant processing time delays during critical operations
Solution Approach 2:
The secure memory controller serves as an intermediary that handles encryption, decryption, and integrity verification transparently. This offloads security processing from the main processor, improving security while minimizing the impact on processing time by performing security operations in parallel or during memory access operations
4Productivity
If secure demand paging system with page replacement strategies is implemented, then memory management efficiency is improved, but device complexity increases
Solution Approach 1:
The secure memory controller implements self-service page replacement strategies by autonomously managing which pages to swap between secure and insecure memory based on usage patterns. This automatic memory management improves efficiency without requiring complex external control mechanisms or increasing overall device complexity
Solution Approach 2:
The system uses feedback from memory access patterns to dynamically adjust page replacement decisions. The secure memory controller monitors usage frequency and automatically replaces least-used pages from secure memory to insecure memory, improving memory management efficiency through adaptive behavior without requiring manual intervention or complex external control
Data Source
AI summary
A secure demand paging system includes a secure internal memory having a table relating physical addresses to virtual addresses, a non-volatile memory, a decryption module and a hash module between the secure memory and the non-volatile memory to allow for decryption and integrity verification of data stored in the non-volatile memory during a transfer to said secure memory and means for connecting the secure memory to a volatile page swap memory such that the non-volatile memory is bypassable during a page swap.