Hardware Secure Element Lookup for Low-Latency Command Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In secure processing systems for automotive applications, existing technologies face challenges in efficiently determining the address associated with a given software routine, leading to latency and robustness issues in message processing due to the complexity of handling encryption and decryption operations within hardware secure modules.
Innovation Solution
A hardware secure element with a microprocessor and non-volatile memory storing software routines, featuring a hardware message handler module that uses a look-up table to associate commands with memory start addresses, allowing direct determination and execution of software routines, thereby reducing latency and improving error handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a hardware secure element uses a traditional software-based method to determine the address of software routines, then the system is easier to implement, but the message processing latency increases and robustness decreases
Solution Approach 1:
The patent pre-calculates and stores the mapping between command identifiers and software routine addresses in a lookup table within the hardware secure element. This preliminary action eliminates the need for time-consuming software-based address determination during message processing, directly reducing latency while maintaining implementation simplicity through hardware acceleration.
Solution Approach 2:
The patent replaces the software-based address determination mechanism with a hardware-based lookup table and decoder circuit. This substitution transitions from a sequential software processing approach to a parallel hardware-based address resolution, significantly reducing processing time and improving robustness without substantially increasing system complexity.
2Reliability
If a hardware secure element isolates the secure processing unit from non-secure elements, then security is improved, but the complexity of communication and coordination increases
Solution Approach 1:
The patent introduces a dedicated communication interface and message format structure as an intermediary between the isolated secure processing unit and non-secure elements. This intermediary layer simplifies coordination by providing standardized message channels with defined protocols, reducing the complexity that would otherwise arise from direct communication while maintaining security isolation.
Solution Approach 2:
The patent segments the communication interface into distinct functional components: message reception, validation, routing, and response generation. This segmentation allows each component to handle specific tasks independently, reducing overall communication complexity while maintaining secure isolation between the secure and non-secure domains.
3Reliability
If a hardware secure element uses a dedicated hardware module for message handling, then message processing robustness improves, but the device complexity increases
Solution Approach 1:
The patent merges the message handling functions directly into the hardware secure element's existing architecture, combining message reception, validation, and routing capabilities within the same hardware module that handles cryptographic operations. This integration improves robustness by ensuring message processing is inherently secure while avoiding the added complexity of separate dedicated hardware modules.
Solution Approach 2:
The patent designs the hardware message handler to perform multiple functions: receiving messages from non-secure elements, validating message formats, determining software routine addresses, and coordinating with the secure processing unit. This multi-functionality improves message processing robustness while reducing overall device complexity by consolidating multiple specialized modules into a single versatile component.
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
A hardware secure element is described. The hardware secure element comprises a microprocessor (106a) and a memory (108), such as a non-volatile memory, having stored a plurality of software routines (HI, H2) executable by the microprocessor (106a), wherein each software routine (HI, H2) starts at a respective memory start address. The hardware secure element comprises also a receiver circuit configured to receive data comprising a command (CMD), and a hardware message handler module (316). The hardware message handler module (316) determines a software routine (HI, H2) to be executed by the microprocessor (106a) as a function of the command (CMD), and provides data (ADDR) to the microprocessor (106a) indicating the software routine to be executed.