Secure Enclave Status Bit for Memory Access Intent Detection
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Solution Overview
Problem
Current secure enclave implementations face storage overhead due to the need for additional data like counters and authentication tags for full cryptographic protection, and the size of the enclave page cache (EPC) cannot be changed at runtime, limiting flexibility in memory management.
Innovation Solution
A computing device that generates memory transactions with secure enclave status bits, computes error-correcting codes, and stores them without the secure enclave status bit, allowing for detection of invalid access intents without relying on range registers or additional storage overhead, using ordinary ECC memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full cryptographic protection is implemented for enclave memory, then security is improved, but storage overhead increases due to additional data like counters and authentication tags
Solution Approach 1:
The patent extracts the access intent indication from traditional cryptographic protection mechanisms. Instead of using counters and authentication tags stored in enclave memory, the invention uses a separate status bit stored in last-level cache metadata to indicate whether memory was accessed from a secure enclave. This removes the storage overhead from enclave memory while maintaining security through a different mechanism.
Solution Approach 2:
The patent introduces an intermediary mechanism between the processor and memory: a status bit stored in last-level cache metadata that indirectly indicates secure enclave access intent. This intermediary allows the system to track security-relevant information without storing it directly in enclave memory, thus avoiding the storage overhead of traditional cryptographic protection mechanisms.
2Reliability
If range registers are used to identify EPC memory, then secure memory identification is achieved, but flexibility is reduced because EPC size cannot be changed at runtime
Solution Approach 1:
The patent makes the secure memory identification dynamic by using virtual memory mappings instead of fixed range registers. The status bit in cache metadata dynamically reflects whether the current memory access originates from a secure enclave, allowing the system to adapt to changing memory configurations and runtime conditions without being constrained by pre-configured EPC sizes.
Solution Approach 2:
The patent creates a universal mechanism that works for all memory locations in the system, not just pre-allocated EPC regions. By setting the status bit based on the actual execution context (whether code is running in a secure enclave), the system can provide secure memory identification for any memory location, regardless of how it was allocated or when the allocation occurred.
Data Source
AI summary
Technologies for software attack detection include a computing device with a processor and a memory external to the processor. The processor originates a memory transaction with an associated secure enclave status bit that indicates whether the memory transaction originated in a secure execution mode, such as from a secure enclave. The processor computes an error-correcting code (ECC) based as a function of memory transaction data and the secure enclave status bit, and performs the memory transaction based on the ECC and the memory transaction data using the memory of the computing device. The processor may store the ECC and the memory transaction data to memory. The processor may load a stored ECC and data from the memory and compare the computed ECC to the stored ECC to detect memory transactions with an invalid secure enclave status bit. Other embodiments are described and claimed.