Secure FPGA Architecture with Non-Bypassable Loader
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Solution Overview
Problem
Conventional key management implementations for field-programmable gate arrays (FPGAs) are susceptible to unauthorized access and tampering, as the decryption key is either stored internally or transferred insecurely, allowing adversaries to capture and misuse the key for unauthorized decryption and modification of configuration data.
Innovation Solution
A secure FPGA architecture that maintains confidentiality by not storing the decryption key locally, using a non-bypassable loader and key management protocol to securely transfer and authenticate the key from an external storage device, employing ephemeral session keys and advanced encryption standards like AES-CCM and AES-CBC for secure decryption and authentication of configuration data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the decryption key is stored internally in the FPGA, then configuration data can be decrypted and loaded, but the key becomes vulnerable to unauthorized access and capture from unsecured storage units
Solution Approach 1:
The decryption key is extracted from the FPGA device and stored externally in a secure key storage unit. This separation removes the key vulnerability from the FPGA's internal unsecured storage, allowing configuration data to be decrypted only when the key is temporarily transferred through the secure JTAG interface for authentication purposes.
2Reliability
If the decryption key is stored externally and transferred through standard interface, then key storage security is improved, but the transfer process becomes vulnerable to interception and capture
Solution Approach 1:
Authentication and decryption occur before any configuration data is loaded into the FPGA. The key is transferred only momentarily to authenticate the configuration data, then immediately removed. This preliminary authentication action prevents the key from being stored in vulnerable states during configuration operations.
Solution Approach 2:
The JTAG interface serves as a controlled intermediary channel for key transfer. By using this standardized interface with known security characteristics and implementing authentication protocols, the system manages the inherent vulnerabilities of external transfer while enabling secure key delivery when needed.
3Reliability
If authentication is performed repeatedly to maintain security, then key confidentiality is maintained, but FPGA performance may be degraded due to additional processing overhead
Solution Approach 1:
Authentication is performed once during the configuration loading process before the FPGA begins operation. The configuration data is authenticated and loaded in a single pass, eliminating the need for repeated authentication during FPGA execution, thus maintaining security without ongoing performance overhead.
Data Source
AI summary
Method and systems using stateful encryption for non-bypassable FPGA configuration including receiving, at an FPGA, FPGA-configuration data comprising a cryptographic state to initialize a cryptographic state of the FPGA, and decrypting, at the FPGA, the FPGA-configuration data, wherein decrypting the FPGA-configuration data yields at least a second cryptographic state and decrypted FPGA-configuration data. Embodiments can include receiving, at the FPGA, a challenge message, processing, at the FPGA, the challenge message to yield at least a third cryptographic state and a response, and transmitting the response from the FPGA.