Secure IC Test Mode Access via Fuse Blowing and Reset Delay
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Solution Overview
Problem
The increasing complexity of integrated circuits (ICs) makes it difficult to access certain portions, such as secure storage and cryptography circuits, for testing, and existing design-for-test techniques may not adequately prevent unauthorized access.
Innovation Solution
Incorporating secure functional units coupled to test access circuitry via fuses that are blown after testing, and using reset circuitry to ensure a full chip reset before entering test mode, thereby preventing unauthorized access by rendering the secure functional units inaccessible.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If test access circuitry is provided to enable testing of secure functional units, then testing capability is improved, but unauthorized access risk increases
Solution Approach 1:
Fuses are blown immediately after testing is completed to prevent unauthorized access. This preliminary action of disabling access right after the useful function (testing) eliminates the security vulnerability while maintaining the testing capability when needed.
Solution Approach 2:
The electrical state of the fuses is changed from conductive (allowing access during testing) to open (preventing access after testing). This parameter change in electrical conductivity enables the transition from a testing state to a secure state.
2Ease of operation
If scan chains are used to provide internal access to secure circuits, then access to inaccessible portions is improved, but security of secure functional units deteriorates
Solution Approach 1:
The fuses connecting scan chains to secure functional units are blown immediately after testing to prevent unauthorized access through the scan chains. This preliminary disabling action maintains security while allowing necessary testing access.
Solution Approach 2:
The secure functional units are extracted from the general testable circuitry by placing them behind fuse-protected connections. This separation allows standard scan chain operation for non-secure circuits while isolating secure units until testing is complete.
3Productivity
If test modes are enabled without delay, then testing efficiency is improved, but data leakage from secure functional units increases
Solution Approach 1:
A reset operation is performed immediately before entering test mode to clear any data that may be temporarily stored outside secure functional units. This preliminary clearing action prevents data leakage while maintaining testing efficiency.
Solution Approach 2:
The reset operation performs a preliminary anti-action by clearing data before it can potentially leak during testing. This preventive measure counteracts the potential harmful effect of data exposure while allowing efficient testing to proceed.
Data Source
AI summary
Methods for enabling a secure test mode, and integrated circuits (IC's) implementing the same are disclosed. An IC may include a secure functional unit that is protected from access from test access circuitry during normal operation. The secure functional unit may be rendered inaccessible the test access circuitry of the IC following a completion of a test that includes testing of the secure functional unit. An embodiment of an IC that includes circuitry to delay entry into a test mode while a chip-level reset is performed is also contemplated. Entry into the test mode may be delayed until all circuitry of the IC has been fully reset in order to clear stored information.