Secure JTAG Interface for ASIC Debugging
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Solution Overview
Problem
Portable data processing systems face a challenge in balancing security against debugging capabilities, as the JTAG port can be exploited to bypass security measures, leading to inefficiencies in creating separate development and commercial versions of chips.
Innovation Solution
A secure JTAG interface is implemented with a Security Module and Test Control Module that allows restricted or unrestricted access based on a password, enabling secure debugging without compromising system security, by altering the security state and using data encryption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the JTAG port is enabled for debugging access, then debugging capability is improved, but system security deteriorates as attackers can bypass password protection
Solution Approach 1:
The JTAG port's access rights are made dynamic through a security state machine that can transition between restricted and unrestricted states. The state changes based on authentication credentials, allowing the system to adapt its security posture rather than maintaining a fixed open or closed state. This resolves the contradiction by enabling debugging only when properly authenticated while maintaining security otherwise.
Solution Approach 2:
A security module acts as an intermediary between the JTAG port and the system resources. This module intercepts and validates access requests, controlling whether debugging operations can proceed. The intermediary enforces authentication requirements and prevents unauthorized access while allowing legitimate debugging when credentials are verified, thus resolving the security-capability conflict.
2Reliability
If separate development and commercial chip versions are created, then security is improved by disabling JTAG in commercial versions, but manufacturing cost and complexity increase
Solution Approach 1:
A single chip design serves multiple functions through conditional access control. The same physical chip can operate in both secure commercial mode and debuggable development mode, with the mode determined by authentication credentials rather than hardware differentiation. This eliminates the need for separate chip versions while maintaining security requirements.
Solution Approach 2:
The system uses parameter changes in authentication credentials to control access behavior. By changing the credential state (present/absent, valid/invalid), the system transitions between secure and debuggable modes without requiring different chip hardware. This single-parameter control approach simplifies manufacturing while maintaining security.
3Reliability
If the JTAG port is disabled after testing, then security is improved, but after-market debugging capability is lost
Solution Approach 1:
The JTAG port maintains dynamic controllability through the security state machine even after initial product deployment. Authorized users can transition the port from restricted to unrestricted state when needed, enabling after-market debugging without compromising ongoing security. The port is never permanently disabled but rather dynamically controlled based on authentication.
Solution Approach 2:
The system implements feedback mechanisms where authentication outcomes directly control JTAG access rights. When valid credentials are provided, the system feedbacks an unrestricted state enabling debugging; when invalid credentials are provided, it feedbacks a restricted state maintaining security. This feedback loop preserves both security and debugging capability as needed.
Data Source
AI summary
The present invention provides a secure JTAG interface to an application-specific integrated circuit (ASIC). In the preferred embodiment the invention operates through the combined efforts of a Security Module (SM) comprising a state machine that controls the security modes for the ASIC, and a Test Control Module (TCM) which contains the JTAG interface. The TCM operates in either a restricted mode or an unrestricted mode, depending on the state of the SM state machine. In a restricted mode, only limited access to memory content is permitted. In an unrestricted mode, full access to memory content is permitted.