Secure Logic Chip Resisting Hardware Trojan Leakage
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Solution Overview
Problem
Current methods are ineffective in preventing data leakage caused by hardware Trojans, particularly data leakage Trojans, which do not alter the normal operation of chips and are difficult to detect, especially in outsourced semiconductor fabrication where malicious modifications can be inserted, and existing countermeasures like runtime monitoring and design for security can be bypassed.
Innovation Solution
A randomized encoding scheme for combinational logics is introduced, using a random logic state generator to encode inputs and outputs through XOR gates or other logic gates, creating dual-rail representations that require both rails to decode, making it difficult for attackers to extract information, and utilizing Quilt Packaging for secure fabrication and integration of chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If runtime monitoring and post-silicon testing are used to detect hardware Trojans, then detection capability is improved, but data leakage Trojans can still bypass these methods as they do not alter normal chip operation
Solution Approach 1:
The patent applies preliminary action by encoding data before it leaves the secure zone through pre-computing random values and preparing encoded representations of data in advance. The random values are generated and stored in buffers before the data transfer occurs, so that when data leaves the secure zone, it is already in an encoded form that requires the random values for decoding, preventing leakage without affecting normal operation.
Solution Approach 2:
The patent uses an intermediary approach by introducing random values as a mediator between the data in the secure zone and the data leaving the secure zone. These random values act as a key that transforms the original data into an encoded form, and without this intermediary random value, the data leaving the zone remains unintelligible, thus preventing leakage while maintaining normal data flow.
2Difficulty of detecting and measuring
If design for security (DFS) methods are used to make design harder to understand, then resistance to reverse engineering is improved, but sophisticated attackers can still procure chips and reverse-engineer the design across multiple fabrication runs
Solution Approach 1:
The patent applies dynamics by making the security mechanism adaptive rather than static. The random values change for each data transfer operation, and the encoding scheme dynamically adjusts based on the current random values. This means that even if an attacker reverse-engineers one instance of the design, the changing random values ensure that the same physical circuit behaves differently in subsequent operations, preventing successful reverse engineering across multiple fabrication runs.
Solution Approach 2:
The patent uses parameter changes by varying the random values that form the basis of the encoding scheme. These random values are parameters that change over time and across different operations, transforming the security properties of the system. Even though the physical circuit remains the same across fabrication runs, the changing parameter values ensure that the logical behavior differs, making reverse engineering ineffective.
3Reliability
If data is encoded using random values before leaving secure zone, then data leakage prevention is improved, but area and power consumption increase due to additional logic circuits and buffers
Solution Approach 1:
The patent applies segmentation by dividing the chip into distinct zones: a secure zone where sensitive data resides and remains encoded, and a non-secure zone where only decoded data can exist. This spatial segmentation allows the encoding logic to be concentrated in the secure zone, limiting the area impact to only the necessary portions of the circuit that handle sensitive data, rather than requiring encoding throughout the entire chip.
Solution Approach 2:
The patent extracts the decoding functionality from the data path by keeping the random values and encoding logic separate from the main data processing circuits. The random values are generated and stored in dedicated buffers, and the encoding/decoding operations are performed by separate logic units that interface with the secure zone, rather than embedding complexity throughout the entire data path. This extraction minimizes the area overhead by concentrating security logic in specific locations.
Data Source
AI summary
In one embodiment, the invention is a method and apparatus for designing combinational logics with resistance to hardware Trojan induced data leakage. The invention solves the untrustworthy fabrication risk problem by introducing a design method such that even when the design is entirely known to an attacker and a data leakage Trojan is injected subsequently, no useful information can be obtained. This invention contains several methods as shown in several embodiments. The methods include randomized encoding of binary logic, converting any combinational binary logic into one with randomized encoding, and partitioning a randomized encoded logic for split manufacturing.