Secure Memory Addressing via Augmented Virtual Addresses

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Solution Overview

Problem

Conventional cybersecurity measures are inadequate in preventing malicious attacks, particularly code injections and control-flow hijacking, due to vulnerabilities in the instruction decoder and memory management within data-processing apparatuses, which can lead to unauthorized access and control of resources.

Innovation Solution

A cybersecure Instruction Set Architecture (ISA) is introduced, where the instruction decoder is isolated from direct access by potentially malicious software, and a virtual memory layout is implemented with a composite augmented virtual address system, ensuring each task has its own secure memory segments and protected code and data spaces, using a safe pointer operator and type words to ensure memory access integrity and control flow integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a uniform read-write random-access memory is used for both program instructions and data, then the data-processing apparatus can operate with simple memory architecture, but the system becomes vulnerable to code injection attacks and control-flow hijacking

Engineering Contradiction:
Improvememory architectureVSAvoidsecurity
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent divides the memory space into distinct segments: a read-only memory segment for storing program instructions and a read-write memory segment for storing data. This segmentation prevents attackers from injecting malicious code into the instruction space, as the instruction memory is inaccessible for writing, while maintaining separate secure spaces for code and data operations.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the instruction decoder is directly accessible by software, then software can efficiently decode and execute instructions, but malicious software can bypass security layers and hijack control flow

Engineering Contradiction:
Improveinstruction execution efficiencyVSAvoidcontrol-flow hijacking
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a memory management unit (MMU) as an intermediary layer between software and the instruction decoder. The MMU enforces memory protection policies, ensuring that only authorized code can access the instruction decoder. This intermediary prevents malicious software from directly manipulating the decoder while maintaining efficient instruction execution for legitimate processes.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If memory areas are marked as non-executable to prevent code injection, then security against code injection is improved, but legitimate memory access patterns may be restricted

Engineering Contradiction:
Improvecode injection preventionVSAvoidmemory access flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies different access permissions to different memory regions: the instruction memory segment is marked as read-only to prevent code injection, while the data memory segment maintains read-write access for legitimate data operations. This localized application of security policies prevents code injection in critical areas while preserving memory access flexibility for legitimate purposes.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11593277B2Method of secure memory addressing
Publication Date: 2023.02.28 KINZINGER AUTOMATION GMBH
  • US11593277B2 patent drawing
  • US11593277B2 patent drawing
  • US11593277B2 patent drawing

AI summary

The problem to be solved is to seek an alternative to known addressing methods which provides the same or similar effects or is more secure. Solution The problem is solved by a method (40) of addressing memory in a data-processing apparatus (10) comprising, when a central processing unit (11), while performing a task (31, 32, 33, 34) of the apparatus (10), executes an instruction involving a pointer (59) into a segment (s, r, d, h, f, o, i, c) of the memory: decoding the instruction by means of an instruction decoder (12), generating a virtual address (45) within the memory by means of a safe pointer operator (41) operating on the pointer (59), augmenting the virtual address (45) by an identifier (43) of the task (31, 32, 33, 34) and an identifier (44) of the segment (s, r, d, h, f, o, i, c), said identifiers (43, 44) being hardware-controlled (42), and, based on the augmented address (45), dereferencing the pointer (59) via a memory management unit (13).