Secure Non-Volatile Memory With Supplemental Bit-Line Detection
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Solution Overview
Problem
Existing non-volatile memories, particularly those using floating gate transistors, are vulnerable to attacks such as laser attacks that alter the reading of sensitive data, and there is a need for additional protection circuits to detect such attacks.
Innovation Solution
A non-volatile memory circuit with a supplemental bit line and polarization circuit that provides distinct current levels for single and multiple memory cell selections, triggering an alarm signal via a supplemental reading amplifier when multiple cells are simultaneously selected, indicating a potential attack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If a non-volatile memory stores security data without power supply, then data retention is improved, but vulnerability to laser attacks worsens
Solution Approach 1:
The patent implements a detection mechanism that is activated before the actual data reading operation. The supplemental bit line and reading amplifier are prepared in advance to detect any abnormal current patterns that would indicate a laser attack, allowing the system to abort the operation before sensitive data is exposed.
Solution Approach 2:
The patent introduces a supplemental bit line and reading amplifier as intermediary components between the memory cells and the external interface. These intermediaries monitor the reading current and can detect attacks without directly exposing the sensitive data, acting as a protective buffer.
2Reliability
If protection circuits are added to detect laser attacks, then security is improved, but device complexity worsens
Solution Approach 1:
The supplemental reading amplifier serves multiple functions: it reads data from supplemental memory cells, detects attack conditions through current monitoring, and generates alarm signals. This multi-functionality reduces the need for separate dedicated components for each function.
Solution Approach 2:
The patent detects attacks by monitoring changes in electrical current parameters on the bit line. The supplemental reading amplifier compares the actual current against expected values and triggers an alarm when deviations indicate an attack, using parameter changes as the detection mechanism.
3Object-affected harmful factors
If multiple word lines are simultaneously activated during an attack, then attack effectiveness is improved, but detection capability worsens
Solution Approach 1:
The patent implements a pre-configured detection system that is ready to counteract multi-line attacks. The supplemental bit line is prepared with appropriate current levels before the attack occurs, and the reading amplifier is configured to detect the specific current patterns that result from simultaneous word line activation.
Solution Approach 2:
The reading amplifier provides feedback about the current state of the bit line to the control logic. When the feedback indicates abnormal current levels consistent with multiple simultaneous activations, the system can abort the operation and trigger an alarm, preventing the attack from succeeding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively detects laser attacks by generating an alarm signal, allowing the system to abort the current program and prevent data breaches.
Implementation Method 1
polarization circuit for polarizing the bit lines with a constant reading current
Implementation Method 2
supplemental polarization circuit for polarizing the supplemental bit line, and a supplemental reading amplifier
Implementation Method 3
each memory cell comprising a floating gate transistor for memorizing a bit value
Implementation Method 4
a method, known as 'fault attack', consists in altering the reading of the memory in such a way to cause some faults during the running of a secure program for locating where are the sensitive data. The fault introduction can be made by laser
Data Source
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AI summary
The invention relates to a non-volatile memory circuit (300) having an attack detector (390) comprising a supplemental bit line (BL') carrying supplemental memory cells (MC') located at the intersection with each word line (WLj). A supplemental polarization circuit (369) polarizes the supplemental bit line (BL'). The supplemental polarization circuit (369) provides a detection current higher than the current drawn by one supplemental memory cell (WC'), and lower than the current drawn by at least two memory cells (WC'). A supplemental reading amplifier (379) connected to the supplemental bit line (BL') can read a first state when one supplemental memory cell (WC') is selected by one word line (WLj) and can read a second state when two or more supplemental memory cells (WC') are simultaneously selected by at least two word lines (WLj). The supplemental reading amplifier (379) providing an alarm signal (ALARM) when the reading corresponds to the second state.