Secure Memory Power Management via Clock Gating and Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In processor-based systems, the secure portions of the system memory map consume excessive power when the processor operates in non-secure mode or issues non-secure memory access transactions, as they remain fully powered for secure memory access transactions, leading to inefficient power management.
Innovation Solution
Implementing a clock gating controller to control clock signals to secure memory portions based on the security type of memory access transactions and a memory retention controller to provide retention-level power when the processor is in non-secure mode, reducing power consumption by gating clock signals and adjusting power levels accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the secure portion of memory remains fully powered for secure memory access transactions, then secure memory access capability is maintained, but power consumption increases during non-secure mode operation
Solution Approach 1:
The patent applies dynamics by making the power state of secure memory portions adjustable rather than fixed. The secure memory portions can dynamically transition between fully powered, retention-mode, and powered-down states based on the processor's current security mode and transaction type, optimizing power consumption while maintaining required functionality
Solution Approach 2:
The patent changes the power state parameter of secure memory portions based on security mode. By monitoring security mode signals and adjusting power delivery accordingly (full power for secure mode, retention power for non-secure mode), the system resolves the contradiction between maintaining secure access capability and reducing power consumption
2Reliability
If the secure portion of memory is kept accessible regardless of security mode, then secure memory access is ensured, but unnecessary power is consumed during non-secure transactions
Solution Approach 1:
The patent applies local quality by differentiating power management for different portions of memory based on security requirements. Secure memory portions receive differentiated power treatment (full power, retention, or off) based on security mode, while non-secure portions operate independently, allowing localized optimization without affecting overall system functionality
Solution Approach 2:
The patent introduces an intermediary power management mechanism that sits between the processor and secure memory portions. This intermediary monitors security mode signals and intermediates power delivery to secure memory, enabling the system to reduce power consumption during non-secure operations while maintaining quick recovery capability for secure access
Data Source
AI summary
Various embodiments include methods and devices for system on chip infrastructure of system on chip infrastructure secure memory access and power management. Some embodiments, include determining whether a processor is performing a secure memory access transaction, and gating a clock signal from being transmitted to a secure portion of a memory in response to determining that the processor is not performing a secure memory access transaction. Some embodiments include determining whether any processor is operating in a secure mode, and transmitting a retention signal to the secure portion of the memory in response to determining that no processor is operating in a secure mode. The retention signal may be configured to set a retention state for the secure portion of the memory.