Secure Memory Erase Sequencing Using Sub-Memory Completion Signals
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Solution Overview
Problem
In secure memory devices, ensuring that sub-memories are erased before the main memory to prevent data exposure when security functions are cleared, as existing methods lack a systematic approach to synchronize the erase operations across multiple memory units.
Innovation Solution
A memory device comprising a main memory, sub-memories, and a controller that receives erase completion signals from each sub-memory to ensure all sub-memories are in a locked state before initiating the erase operation on the main memory, using multiplexers and flip-flops to generate and manage erase completion signals, and an AND gate to enable the main memory erase only when all sub-memories have completed their erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the main memory is erased before sub-memories, then the erase operation can be completed quickly, but the sub-memories may enter an unlocked state and expose secure data
Solution Approach 1:
The patent applies preliminary action by requiring sub-memories to be erased before the main memory. The controller monitors erase completion signals from sub-memories and only initiates the main memory erase operation after all sub-memories have completed their erase operations, ensuring security control signals are cleared first and preventing data exposure.
2Reliability
If the sub-memories are erased before the main memory, then data security is maintained, but the erase operation sequence becomes more complex
Solution Approach 1:
The patent implements feedback by having sub-memories generate erase completion signals that are monitored by the controller. The controller uses this feedback information to determine when it is safe to proceed with erasing the main memory, creating an automated control mechanism that manages the complex erase sequence without requiring manual intervention.
3Reliability
If the controller monitors erase completion signals from all sub-memories, then data exposure is prevented, but the control mechanism becomes more complex
Solution Approach 1:
The patent uses an intermediary approach by introducing a controller that acts as a mediator between sub-memories and the main memory. The controller receives erase completion signals from sub-memories and uses these signals to control when the main memory erase operation should proceed, simplifying the overall control logic while maintaining security.
Data Source
AI summary
A memory device includes a main memory, a first sub-memory and a controller. When the first sub-memory is erased, the first sub-memory generates a first erase completion signal. The controller receives an erase signal to erase the main memory. The controller performs an erase operation on the main memory according to the erase signal and the first erase completion signal.