Secure Memory Device Fault Detection via Register Amplification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Secure memory devices, such as smart cards, face challenges in detecting faults injected by malicious attacks, leading to data loss or corruption, and existing solutions require external detection devices, increasing size and power consumption while failing to detect small faults effectively.
Innovation Solution
A data processing device with a first and second register unit and a data handling unit that generates a detectable error in secure data when a fault is injected, allowing self-detection and countermeasures without reducing performance or increasing size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external detection devices are used to detect faults in secure data, then detection capability is improved, but device size and power consumption increase
Solution Approach 1:
The patent merges the fault detection function with the existing data processing unit by using the same register units and data paths. The second register unit performs both normal data processing and fault amplification/detection functions, eliminating the need for separate external detection devices and reducing overall device size.
Solution Approach 2:
The data processing device performs self-detection of faults using its own internal resources. The second register unit amplifies faults in the data it processes, allowing the device to detect faults injected into secure data without requiring external detection equipment.
2Reliability
If external detection devices are used to detect faults in secure data, then detection capability is improved, but power consumption increases
Solution Approach 1:
The fault detection function is merged with the data processing function, using the same power supply and processing units. This eliminates the need for additional power consumption associated with separate external detection devices.
Solution Approach 2:
The device uses its own processing units to perform fault detection during normal operation, leveraging existing power consumption rather than requiring additional power from external detection equipment.
3Reliability
If fault detection mechanisms are added to secure memory device, then security is improved, but operational speed decreases
Solution Approach 1:
The fault detection mechanism operates continuously during normal data processing without requiring separate detection cycles. The second register unit amplifies faults in real-time as data is processed, maintaining operational speed while providing continuous security monitoring.
Solution Approach 2:
By combining fault detection with data processing operations, the system performs both functions simultaneously rather than sequentially, avoiding the speed penalty that would result from separate detection phases.
4Measurement precision
If fault amplification is applied to detect small faults, then detection precision is improved, but data processing complexity increases
Solution Approach 1:
The second register unit applies fault amplification selectively only when needed for detection purposes, rather than continuously processing all data through complex amplification routines. This partial application maintains precision for fault detection while minimizing overall processing complexity during normal operations.
Data Source
AI summary
A data processing device includes a first register unit, a second register unit and a data handling unit. The first register unit generates an address signal based on a first control signal. The address signal points to a region in an external storage device where first data is stored. The second register unit receives the first data output from the external storage device, generates second data based on the first data and a second control signal, and selectively generates a detectable error in the second data according to an operating mode when a fault is injected into the first data. A bit number of the detectable error in the second data is larger than a bit number of the fault injected into the first data. The data handling unit selectively processes the second data depending on whether the detectable error is generated.