Secure Memory Reset Circuit for Fast Voltage Glitch Detection
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Solution Overview
Problem
Existing secure chips are vulnerable to side channel voltage glitch attacks due to the slow response of conventional power reset circuits, which fail to detect rapid and brief voltage drops, and are unable to operate under extreme voltage conditions, allowing hackers to access confidential data.
Innovation Solution
A glitch protection system that includes a first reset-detector and a glitch-detector coupled to the power-on-reset block, capable of detecting drops in supply voltage with different slope magnitudes and times, providing a global-reset signal to ensure safe reset under all conditions, without interfering with existing CMOS voltage level reset-detectors or brown-out detectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional power reset circuits are used, then the chip can detect slow voltage drops, but the response time is too slow to detect rapid voltage glitches
Solution Approach 1:
The power reset circuit is segmented into two independent detection paths: a conventional slow-response detector for gradual voltage drops and a new fast-response glitch detector for rapid glitches. Each detector is optimized for its specific detection task, allowing the system to handle both slow and fast voltage variations simultaneously without interference.
Solution Approach 2:
A retention circuit acts as an intermediary between the fast glitch detector and the reset mechanism. When a glitch is detected, the retention circuit temporarily stores this information and triggers the reset, bridging the gap between the ultra-fast glitch detection and the slightly slower reset execution, ensuring no glitch escapes undetected.
2Reliability
If conventional detectors operate under extreme voltage conditions, then they may fail to detect glitches, but protecting against them requires additional circuitry
Solution Approach 1:
The glitch detector is designed with local quality optimized for extreme voltage conditions, using circuit elements and detection thresholds specifically tailored for rapid voltage transitions to 0V or negative voltages. This specialized local design allows reliable glitch detection under extreme conditions without requiring complete redesign of the entire power reset system.
3Reliability
If a fast glitch detector is added, then glitch detection capability improves, but the system complexity increases
Solution Approach 1:
The retention circuit serves multiple functions: it stores glitch detection information, coordinates the reset timing, and interfaces between the fast glitch detector and the reset mechanism. By merging these functions into a single circuit block, the design minimizes the increase in overall system complexity while achieving reliable fast glitch detection.
Data Source
AI summary
A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global-reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.