Secure Memory Repair Circuits Using Random-Bit Output Masking
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Solution Overview
Problem
The integration of embedded RAM in integrated circuits leads to high defect probability, affecting chip yield and impairing testability, and existing repair mechanisms can make reverse-engineering feasible.
Innovation Solution
A memory circuit design incorporating a memory array with first and second memory cells, where second cells store repair bits that can output random bits, making the circuit unpredictable and difficult to reverse-engineer, thereby enhancing security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If embedded RAM is integrated into ICs to improve integration density, then more components can be integrated into a given area, but the defect probability increases and chip yield decreases
Solution Approach 1:
The patent segments the memory array into functional units with dedicated repair circuits for each segment. Each segment has its own repair mechanism that operates independently, allowing localized repair without affecting the entire memory array. This segmentation enables better defect management while maintaining high integration density.
Solution Approach 2:
The patent changes the state of memory cells from standard RAM to one-time programmable (OTP) memory cells with fixed contents after programming. This parameter change in memory cell behavior enables permanent storage of repair information and prevents subsequent modification, thereby improving reliability while maintaining integration density.
2Reliability
If conventional repair mechanisms are used in memory circuits, then defects can be corrected, but the circuit becomes vulnerable to reverse-engineering
Solution Approach 1:
Instead of using conventional repair mechanisms that store repair information in accessible locations, the patent inverts the approach by embedding repair information directly into the memory array structure itself. The repair bits are stored in dedicated memory cells within the array, making the repair mechanism transparent and difficult to detect or reverse-engineer.
Solution Approach 2:
The patent introduces an intermediary repair circuit layer between the memory array and the external interface. This intermediary layer handles all repair operations internally and presents a simplified interface to the outside world, hiding the complexity of the repair mechanism and preventing reverse-engineering while maintaining defect correction capability.
3Reliability
If repair bits are stored in memory cells to enable defect correction, then the circuit can repair itself, but the testability of the circuit is impaired
Solution Approach 1:
The patent extracts the repair information storage function from the main memory array by using dedicated repair memory cells separated from the primary data storage cells. This extraction allows independent testing of the repair mechanism without interfering with the main memory array functionality, thereby improving testability while maintaining self-repair capability.
Solution Approach 2:
The patent implements preliminary testing and configuration of repair bits before they are programmed into the memory array. The repair mechanism is configured and tested in advance, allowing verification of repair functionality independent of the main memory operations. This preliminary action enables better testing and measurement of the repair system.
Data Source
AI summary
A memory circuit includes a memory array comprising first memory cells and second memory cells, each of the first memory cells configured to store a data bit, and each subset of the second memory cells configured to store repair bits, the repair bits indicating a location of a corresponding first memory cell and a random bit; register circuits, the register circuits configured to transfer or latch the plurality of repair bits; a compare circuit coupled to the register circuits, the compare circuit configured to provide a match signal, in response to determining that an address signal matches the location of the corresponding first memory cell indicated by the repair bits; and a multiplexer coupled to the compare circuit, the multiplexer configured to output the random bit instead of the data bit stored by the corresponding first memory cell, based on the match signal.