Secure Memory Segmentation for Parallel Control and Operation
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Solution Overview
Problem
Conventional memory management systems for integrated circuits (ICs) face inefficiencies in managing secure memories, leading to potential data corruption, security compromises, and significant downtime due to halted memory operations and reset requirements during self-test and fault detection processes.
Innovation Solution
The proposed solution involves a memory management system that executes memory operations on one secure memory element while simultaneously performing control operations, such as error detection, fault injection, or power profile masking, on another secure memory element. After these operations, the data from the first secure memory element is copied to the second, maintaining data integrity and reducing downtime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory operations are halted during self-test and fault detection processes, then security and reliability are improved, but downtime increases
Solution Approach 1:
The secure memory is divided into multiple memory elements, allowing the system to perform control operations on one element while memory operations continue on other elements. This segmentation enables parallel processing where security testing and normal memory operations occur simultaneously on different memory units, thus maintaining security without halting overall system operations.
Solution Approach 2:
The system maintains continuous memory operations by executing control operations on a second memory element while the first memory element remains operational for normal memory access. This ensures that useful actions (memory operations) continue uninterrupted while security testing proceeds in parallel, eliminating the need to halt operations for self-test procedures.
2Reliability
If reset operations are performed during fault detection, then reliability is improved, but productivity decreases
Solution Approach 1:
By segmenting the secure memory into multiple elements, the system can isolate fault detection and reset operations to specific memory elements rather than requiring system-wide resets. This allows other memory elements to continue operating normally, maintaining productivity while ensuring reliability through targeted fault handling.
Solution Approach 2:
The system performs preliminary control operations including error detection and fault injection testing on the second memory element before actual memory operations are executed. This preliminary testing ensures that fault detection mechanisms are validated without interrupting the main memory operations on the first element, thus maintaining productivity while ensuring reliability.
3Reliability
If control operations are executed on secure memory, then security is improved, but memory operation efficiency decreases
Solution Approach 1:
The secure memory is segmented into multiple elements that can operate independently. Control operations for security enhancement are executed on one element while memory operations continue on other elements, allowing security improvements without sacrificing memory operation efficiency. This parallel architecture enables both security and performance to coexist.
Solution Approach 2:
The system maintains continuous memory operation efficiency by executing control operations on a separate memory element from the one being accessed for normal operations. This ensures that security-enhancing control operations do not interfere with or halt productive memory operations, as both types of operations proceed simultaneously on different memory units.
Data Source
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Figure 3A
AI summary
An integrated circuit (IC) includes first and second secure memory elements storing identical data and a memory management system that executes a memory operation on the first secure memory element and a control operation on the second secure memory element simultaneously. The control operation is associated with safety of the IC and is executed to enable error detection in the second secure memory element, fault injection for the second secure memory element, masking of a power profile associated with the memory operation, or a combination thereof. After the execution of the memory operation and the control operation, the memory management system copies the data of the first secure memory element to the second secure memory element to maintain sanity of the second secure memory element.